Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7426
標題: FPGA設計與實作低成本高效能的緊縮型AES加解密處理器
FPGA Implementation and Design of a Low-Cost and High Performance Compact AES Processor
作者: 陳奕達
Chen, I-DA
關鍵字: AES
加解密
low cost
high performance
FPGA
低成本
高效能
出版社: 電機工程學系所
引用: [1] William Stallings, "Cryptography and Network Security," Prentice-Hall, 2003. [2] National Institute of Standards and Technology (NIST), "Advanced Encryption Standard (AES)," Federal Information Processing Standards (FIPS) Publication 197, November 2001. [3] V. Fischer and M. Drutarovsky, "Two methods of Rijndael implementa-tion in reconfigurable hardware," in Proc. CHES 2001, Paris, France, May 2001, pp. 77-92. [4] F. Gurkaynak, D. Hug, and H. Kaeslin, "A 2 Gb/s Balanced AES Cryp-to-Chip Implementation," GLSVLSI 2004. [5] C. Paar, "Efficient VLSI Architectures for Bit Parallel Computation in Galois Fields," PhD Thesis, Institute for Experimental Mathematics, Uni-versity of Essen, Germany, 1994. [6] C. Paar, "Fast finite field arithmetic for VLSI design." In 3rd Bene-lux -japan Workshop on Coding and Information Theory, page 7, Institute for Experimental Mathematics, University of Essen, Germany, August 30 1993. [7] C. Paar, "A parallel Galois field multiplier with low complexity based on composite fields," In 6th Joint Swedish_Russian Workshop on Information Theory, pages320-324, Molle, Sweden, August 22-27 1993. [8] Daemen, J., and Rijmen, V, "AES proposal: Rijndael', version 2," March 1999, http://www.nist.gov/aes [9] S.-F. Hsiao and M.-C. Chen, "Efficient substructure sharing methods for optimising the inner-product operations in Rijndael advanced encryption standard," IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 5, September 2005. [10] Rijmen, V. "Efficient implementation of the Rijndael S-box," http://www.iaik.tugraz.ac.at/research/krypto/AES/old/_rijmen/rijndael/sbox.pdf [11] Wolkerstorfer, J., Oswald, E., and Lamberger, M. "An ASIC implementation of the AES SBoxes," CT-RSA 2002, San Jose, CA, USA, February 2002, (Lect. Notes Comput. Sci., 2271), pp. 67-78 [12] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A compact Rijndael hardware architecture with S-Box optimization," in Proc. ASIACRYPT 2001, Gold Coast, Australia, Dec. 2000, pp. 239-254. [13] T. Good and M. Benaissa, "Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)," IET Inf. Secur., 2007, 1, (1), pp. 1-10 [14] A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao and P. Rohatgi, "Efficient Implementation of Rijndael Encryption with Composite Field Arithmetic," Proc. CHES 2001, pp. 171-184, Paris, France, May 2001. [15] Xinmiao Zhang; K.K. Parhi, "High-speed VLSI architectures for the AES algorithm," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 12, Issue 9, Sept. 2004 Page(s):957 - 967 [16] Xinmiao Zhang; K.K. Parhi, "On the Optimum Constructions of Com-posite Field for the AES Algorithm," FOR SUBMISSION TO TCAS-II [17] T. Jarvinen, P. Salmela, P. Hamalainen, and J. Takala. Efficient byte permutation realizations for compact AES implementations. In Proc. 13th European Signal Processing Conf. (EUSIPCO 2005), Antalya, Turkey, Sept. 4-8, 2005. [18] V.Fischer, M. Drutarovsky, P Chodowiec, F. Gramain, "InvMixColumn Decomposition and Multilevel Resource Sharing in AES Implementations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 13, NO. 8, AUGUST 2005 [19] Hodjat, A., and Verbauwhede, I. "A 21.54 Gbits/s fully pipelined AES processor on FPGA," Proc. 12th Annual IEEE Symp. On Field-Programmable Custom Computing Machines (FCCM'04), Napa, CA, USA, April 2004, pp. 308-309 [20] Zambreno, J., Nguyen, D., and Choudhary, A. "Exploring area/delay tradeoffs in an AES FPGA implementation," FPL 2004, Antwerp, Belgium, 2004, (Lect. Notes Comput. Sci., 3203), pp. 575-585 [21] K. U. Jarvinen, M. T. Tommiska, and J. O. Skytta, "A fully pipelined memoryless 17.8 Gbps AES-128 encryptor," in Proc. Int. Symp. Field- Pro-grammable Gate Arrays (FPGA 2003), Monterey, CA, Feb. 2003, pp. 207-215. [22] G. P. Saggese, A. Mazzeo, N. Mazocca, and A. G. M. Strollo, "An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm," in Proc. FPL 2003, Portugal, Sept. 2003. [23] F. Standaert, G. Rouvroy, J. Quisquater, and J. Legat, "Efficient im-plementation of Rijndael encryption in reconfigurable hardware: Improve-ments & design tradeoffs," in Proc. CHES 2003, Cologne, Germany, Sept. 2003. [24] T. Good and M. Benaissa "Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)," IET Inf. Secur., Vol. 1, No. 1, March 2007
摘要: 2001 年 NIST (National Institute of Standards and Technology) 公開發表進階加解密的標準(AES)為新的加解密標準,且使用在多種應用與協定上。 因此,採用何種適合的硬體架構設計方式,並且考慮到成本與效能,為重要的一環。本篇論文中,我們則是採用複合場的型式來處理 SubBytes/InvSubBytes 轉換,以降低運算複雜度及節省硬體面積。於本篇論文中,在 SubBytes/InvSubBytes 的部份,則是由[12,15]提出的架構做修改,而 MixColumns 和 InvMixColumns 轉換部份,則是修改了架構使得能夠利於管線式的實作方式。 我們使用 Xilinx 公司提供的 FPGA 平台來實現全管線式架構的 AES 加解密處理器,使用管線與子管線式的搭配,其傳輸延遲一共為 71 個時脈週期; 而在非迴授模式下使用 XCV1000e-8 FPGA 來驗證我們提出的 AES 架構,其資料處理量可達 22.068 Gbits/s,整體硬體效能為 2.026。
In 2001, NIST(National Institute of Standards and Technology) proposed the AES(Advanced Encryption Standard) which is a new cryptography standard. The AES can be used for many applications and protocols. Therefore, it is very important that which kind of the suitable architectures we can adopt, then we must consider the cost and the efficiency of the AES hardware. We use the compose-field based algorithm to process the SubBytes/InvSubBytes transformation that can reduce the operation complexity and save the hardware area. In this report, we improve the part of the architecture in the SubBytes/InvSubBytes transformation which is derived from [12,15]. Then, we adjust the architecture of the MixColumns/InvMixColumns transformation to be suitable for the pipelined design. We use the Xilinx FPGA platform to implement the full pipelined AES architecture. The proposed AES design needs 71 cycles latency. In the non-feedback mode, the throughput of the architecture targeted on the XCV 1000e-8bg560 FPGA can achieve 22.068 Gbit/s and the hardware efficiency is 2.026.
URI: http://hdl.handle.net/11455/7426
其他識別: U0005-0907200716313300
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0907200716313300
Appears in Collections:電機工程學系所

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