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FPGA Implementation and Design of a Low-Cost and High Performance Compact AES Processor
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|摘要:||2001 年 NIST (National Institute of Standards and Technology) 公開發表進階加解密的標準(AES)為新的加解密標準，且使用在多種應用與協定上。 因此，採用何種適合的硬體架構設計方式，並且考慮到成本與效能，為重要的一環。本篇論文中，我們則是採用複合場的型式來處理 SubBytes/InvSubBytes 轉換，以降低運算複雜度及節省硬體面積。於本篇論文中，在 SubBytes/InvSubBytes 的部份，則是由[12,15]提出的架構做修改，而 MixColumns 和 InvMixColumns 轉換部份，則是修改了架構使得能夠利於管線式的實作方式。
我們使用 Xilinx 公司提供的 FPGA 平台來實現全管線式架構的 AES 加解密處理器，使用管線與子管線式的搭配，其傳輸延遲一共為 71 個時脈週期; 而在非迴授模式下使用 XCV1000e-8 FPGA 來驗證我們提出的 AES 架構，其資料處理量可達 22.068 Gbits/s，整體硬體效能為 2.026。|
In 2001, NIST(National Institute of Standards and Technology) proposed the AES(Advanced Encryption Standard) which is a new cryptography standard. The AES can be used for many applications and protocols. Therefore, it is very important that which kind of the suitable architectures we can adopt, then we must consider the cost and the efficiency of the AES hardware. We use the compose-field based algorithm to process the SubBytes/InvSubBytes transformation that can reduce the operation complexity and save the hardware area. In this report, we improve the part of the architecture in the SubBytes/InvSubBytes transformation which is derived from [12,15]. Then, we adjust the architecture of the MixColumns/InvMixColumns transformation to be suitable for the pipelined design. We use the Xilinx FPGA platform to implement the full pipelined AES architecture. The proposed AES design needs 71 cycles latency. In the non-feedback mode, the throughput of the architecture targeted on the XCV 1000e-8bg560 FPGA can achieve 22.068 Gbit/s and the hardware efficiency is 2.026.
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