Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7561
標題: 具有高效能且高頻壓控振盪器的除小數頻率合成器之設計
Design of a Fractional-N Frequency Synthesizer with High-performance and High-Frequency Voltage-Controlled Oscillators
作者: 凃嘉杰
Tu, Chia-Chieh
關鍵字: Frequency Synthesizer
頻率合成器
出版社: 電機工程學系所
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摘要: 本論文主要探討高頻高效能的壓控振盪器,與應用鎖相迴路技術實現直接除小數的頻率合成器,主要可分成三部分。第一部分先介紹振盪器的概念、振盪原理,以及內部的元件和相位雜訊的定義;此外,比較數個基本型電感-電容式的振盪器,最後介紹四相位輸出的電感-電容式壓控振盪器。 在本論文第二部分中將利用積體化變壓器的架構實現可調電感的技術並應用於壓控振盪器中,並對其進行分析。本電路架構以TSMC 0.18uM CMOS 製程實現。中心頻率操作於6.42GHz,可調頻率範圍約為600MHz,在1MHz偏移處相位雜訊約為-122.85dBc/Hz,總功率消耗為28mW。 第三部分主要介紹以電感-電容式振盪器的概念實現高頻高效能的壓控振盪器;其中包括二個注入鎖定式四相位壓控振盪器架構和一個電感式耦合分配振盪器。其中,電感式耦合分配振盪器改善了以往利用被動元件-電感,產生四相位的缺點-閃爍雜訊,而利用被動元件-電感,產生四相位。而注入鎖定式振盪器的部分,主要以高頻的壓控振盪器利用注入鎖定的原理結合第一級預除器,並產生四相位輸出。此三個電路架構皆以TSMC 0.18 製程實現,輸出頻率約為9-10GHz。 最後一部分將利用前面提到的注入鎖定式振盪器架構實現一高頻的直接除小數頻率合成器。本頻率合成器以TSMC 0.13 uM RF CMOS製程實現,輸出頻率為20.2GHz,參考頻率為157MHz,除率為128.5,總消耗功率為68mW,總面積為1.13*1.6mm2。
This thesis mainly describes a direct fractional-N frequency synthesizer with a phase-lock-loop technique by using high-frequency and high-performance oscillators. The thesis could be divided into four parts. The first part is about oscillator fundamentals, inner devices and the definition of phase noise. Furthermore, we also compare several basic LC oscillators, and quadrature( four-phase ) oscillator design is described. The second part of this thesis introduce the integrated transformer to achieve inductance-tuning technique in LC-oscillators. The transformer based VCO topology is fabricated in TSMC 0.18 uM CMOS technology. The center frequency is at 6.42GHz, and frequency tuning range is about 600MHz. The phase noise at 1MHz is about -122.85dBc/Hz. The total power consumption is 28mW. The third part mainly introduces high-frequency and high-performance oscillators based on LC-VCOs. There are two injection-locked quadrature- VCOs (QVCO) and an inductor-coupled distributed oscillator which could also generate quadrature signals. The distributed oscillator uses passive components-inductors for enforcing signal coupling, instead of active components-MOSFETs for eliminating flicker noise from active components. The injection-locked oscillator contains a high-frequency VCO and a prescaler. Based on injection-locked theory, the output frequency of prescaler will be locked by a multiple frequency of VCO and generate quadrature signals. The three topology are fabricated in TSMC 0.18 technology, and output frequencies range from 9 to 10GHz. In the last part, we achieve a high-frequency fractional-N frequency synthesizer by mainly using a VCO and an injection-locked frequency divider. The frequency synthesizer is fabricated in TSMC 0.13 uM RF CMOS technology. Its output frequency is at about 20.2GHz, and its reference frequency is about 157MHz. The division ratio is 128.5, the total power consumption is 68mW, and the total area is 1.13*1.6mm2.
URI: http://hdl.handle.net/11455/7561
其他識別: U0005-2008200714462400
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2008200714462400
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