Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7611
標題: 無記憶體直接數位式頻率合成器之設計與分析
Design and Analysis of ROM-Less Direct Digital Frequency Synthesizers
作者: 溫錦炘
Wen, Jing-Shing
關鍵字: Frequency Synthesizer
頻率合成器
出版社: 電機工程學系所
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摘要: 頻率合成器大致可分為鎖相迴路及直接數位頻率合成器兩種結構形式,而本篇論文採用直接數位頻率合成器,也大致介紹直接數位頻率合成器的原理及不同架構的分別,最後也有提出異於傳統架構的兩個無記憶體式直接數位頻率合成器,第一架構是圍繞在非線性數位至類比轉換器上,因為我們將傳統式結構中的記憶體去除,改成以非線性數位至類比轉換器來實現,在考量到晶片實作上及整體效能的改進,進而將非線性數位至類比轉換器的架構改進成分段式數位至類比轉換器的架構,透過實驗證明了確實在效能上有所改進。儘管第一個晶片已經實現一個無記憶體的直接數位頻率合成器,我們又提出使用translinear的作法,這樣的作法也是一種無記憶體的實現方法,並且可以實現的特性是更加的好,而面積上比分段式非線性數位至類比轉換器的架構,可以省去龐大的微調數位控制電路,整體的特性更是進一步的提升,各方面來說都有很大的效果,唯獨製程的選擇是不得已。除此之外,此兩個晶片所使用的分段式數位至類比轉換器也是本論文的研究重點之一,因為整體架構我們除了節省面積之外,也朝向更高速的設計方式來實現直接數位頻率合成器,所以需要一個高速的數位至類比轉換器,論文中也有詳盡的去研究如何去設計出高速且高精確度的數位至類比轉器。 因此本篇論文將有三顆晶片實作驗證,第一顆晶片實作為一個每秒十億取樣率十位元的電流式CMOS數位類比轉換器研究,所使用的製程為0.18um CMOS,電路面積為1.4mm × 1.4mm,功率消耗約為131mW。量測結果可操作至850MHz,線性度INL、DNL皆在5LSB以下,THD量測值與理想值比較後,在高速率下皆在0.3%以下。而第二顆晶片為使用分段式數位至類比轉換器實現的直接數位頻率合成器的研究,但論文中的量測結果不佳,因此我們嘗試以不同的微調電路去重新實驗,同樣使用0.18um CMOS製程,電路面積為1.7mm × 1.6mm,功率消耗約為271mW。模擬結果電路可操作至1GHz,SFDR最高可達55dB。最後一顆晶片實作是利用translinear電路實現的直接數位頻率合成器,使用0.35um SiGe 製程,功率消耗約為205 mW,模擬結果電路可操作至500MHz,SFDR可達60 dB以上。
There are two kinds of frequency synthesizers include of phase lock loop based and direct digital frequency synthesizer (DDFS). In this thesis, direct digital frequency synthesizer is adopted and the principle of DDFS is introduced generally. Then, there are some comparisons about different structures. Finally, we propose two new structures different from conventional ones. The first one is major on non-linear digital to analog converter (DAC). To think about chip design and improve efficiency of all, we use segmented DAC to replace ROM of conventional ones. According to our experiment result, it prove the new structure can reach our goal. In the second one we propose an other new approach used translinear circuit with better performance. Compared with the first one, it can save the area which don’t use the fine tune decoder circuit and improve the over all efficiency. The only one drawback is the limitation of the technology. Besides, the DAC structure used in the two DDFS is an other important point of this thesis. When we design the all structure, we demand not only saving area but also more higher speed to out work. So we also have completed research about how to design a high speed DAC. Thus, there are three chips designed in this thesis. The first one is a research about 10bit 1GS/S Current-Steering DAC. The chip is implemented in 0.18um CMOS technology with the die area 1.4mm × 1.4mm and the power consumption is about 131mW. The measurement result of operation speed is up to 850MHz,and linearity INL、DNL are both under 5LSB. THD is measured under 0.3% in high speed operation. The second ones discussed a high-speed ROM-less direct digital frequency synthesizer realized by a segmented non-linear DAC. Because the measurement of this thesis is not good, we try another fine tune circuit to test again. The chip is implemented in 0.18um CMOS technology with the die area 1.7mm × 1.6mm and the power consumption is about 271mW. The measurement result of operation speed is up to 1GHz,and the maximum of SFDR is 55 dB. The last chip is a ROM-less direct digital frequency synthesizer realized by translinear circuit and implemented in 0.35um SiGe technology with power consumption is 205mW. The measurement result of operation speed is up to 500MHz,and SFDR is 60dB up .
URI: http://hdl.handle.net/11455/7611
其他識別: U0005-2208200714162000
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2208200714162000
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