Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8128
標題: 應用背閘極耦合及線性化增益技巧之SiGe BiCMOS四相位壓控振盪器設計
A Linearized-Kvco SiGe BiCMOS Quadrature VCO with Back-gate Coupling Technique
作者: 張裕鑫
Chang, Yu-Hsin
關鍵字: QVCO
四相位壓控振盪器
low power linearized
back-gate coupling
voltage- level-shift circuitry
低功耗線性化
背閘極耦合
電位偏移電路
出版社: 電機工程學系所
引用: Reference [1] M. H. Seyedi, M. Dousti, F. Temcamani, and J. L. Gautierassoud, “A fully differential low phase noise and extra linear VCO design in SiGe BiCMOS technology,” in ICTTA 3rd International Conference, pp. 1-5, April 2008. [2] H. M. Chen, Y. D. Junang, J. C. Lin, and S. L. Jang, “A 5.6 GHz balanced Colplitts QVCO with back-gate coupling technique,” in EDSSC2007 Conference, pp. 965-967, Dec. 2007. [3] H.-R. Kim, S.-M. Oh, S.-D. Kim, Y.-S. Youn, and S.-G. Lee, “Low power quadrature VCO with the back-gate coupling,” in Proceedings of the 29th European Solid-Stage Circuits Conference 2003, pp. 699 - 701, Sept. 2003. [4] H. R. Kim, C. Y. Cha, S. M. Oh, M. S. Yang, and S. G. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 952-955, June 2004. [5] Behzad Rezavi, Chapter 14 in Design of Analog CMOS Integrated Circuit, McGraw-Hill Book Co. Press, Preview edition, 2000. [6] Behzad Razavi, RF Microelectronics, Prentice Hall Inc Press, 1998. [7] N. Mitsuhiro, N. Toshinori, M. Yuuichiro, S. Tomoaki, K. Shigeru,O. Yukihito, and T. Akira, “Back gate effects on threshold voltage sensitivyity to SOI thickness in fully-depleted SOI MOSFETs,” IEEE Electron Device Letters, vol. 22, no.1, Jan. 2001. [8] M. J. Chen, J. S. Ho, T. H. Huang, C. H. Yang, Y. N. Jou, and T. Wu, “Back-gate forward bias method for low-voltage CMOS digital circuit,” IEEE Transactions on Electron Devices, vol. 43, no. 6, June 1996. [9] N. J. Oh, and S. G. Lee, “11-GHz CMOS differential VCO with back-gate transformer feedback,” IEEE Microwae and Microwave Components letters, vol. 15, no. 11, Nov. 2005. [10] W. F. Chung, and K. K. M. Cheng, “A super-harmonic back-gate coupled quadrature VCO in standard CMOS process,” in Proceddings of Asia- Pacific Microwave Conference 2007. [11] S. Kurachi, T. Yoshimasu, H. Liu, N. Itoh, and K. Yonemura, “A SiGe BiCMOS VCO with highly linear Kvco for 5-GHz-band wireless LANs,” IEICE Transactions on Electronics, vol. E90-C, no. 6 , pp. 1128-1233, June 2007. [12] P. Andreani, and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905 - 910, June 2000. [13] S. M. Sze, Chapter 6 in Semiconductor Device-Physics and Technology, 2nd edition, Wiley, New York, 2001. [14] Sedra Smith, Chapter 5 in Microelectronic Circuits, 3rd edition, Sanuders College Publishing, 2001. [15] V. Kakani, F. F. Dai, and R. C. Jaeger, “A 5 GHz low-power series coupled BiCMOS quadrature VCO with wide tuning range,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 6, pp. 457-459, Jun. 2007. [16] K. G. Park, C.Y. Jeong, J.W. Park, J.W. Lee, J.G. Jo, and C. Yoo. “Current Resuing VCO and Divide-by-Two Frequency Divider for Quadrature LO Generation,” IEEE Microwave and Wireless components letters, vol. 18, no. 6, June 2008.
摘要: 摘要 在無線網路應用上,壓控振盪器對收發機的設計而言是一個重要的電路。壓控振盪器的特性可以影響收發機整體的性能,甚至影響整體電路是否達到所需之系統規格。低相位雜訊及低功耗對壓控振盪器的設計來說是重要的要求。除了這兩項指標外,壓控振盪器增益(Kvco)的線性度也是一個重要的性能。在鎖相迴路中達到穏定時間是重要的而此項特性會受壓控振盪器增益的線性度所影響。此外,在現代通信系統中,常使用正交訊號於調變解調技巧中;在各種產生正交本地振盪訊號的方法中,又以四相位壓控振盪器具有較低功耗及較佳之相位雜訊等優勢。 本研究的目的即在設計一5GHz的低功耗線性化四相位壓控振盪器。為了達到低功耗的目的,一般用於四相位壓控振盪器中的耦合電晶體被以背閘極耦合方式所取代。此外我們的電路採用一新穎的共振電路線性化技巧來改善增益之線性度。此共振腔由四對PN接面式可變電容器及一個螺旋型電感所組成,並有一個電位偏移電路用來適當決定每對可變電容之偏壓點。 我們設計的電路由國家系統晶片中心協助製作於台積電0.35µm矽鍺BiCMOS製程上。我們的模擬結果驗證了所設計的四相位壓控振盪器之性能。此電路僅有1.5倍Kvco比率,操作於5GHz頻段而於1MHz頻差處可達到-116dBc/Hz相位雜訊。核心電路在3V電壓供應下消耗3.46mA電流。晶片大小為0.605 x 0.745 mm2。
Abstract A voltage-controlled oscillator (VCO) is a critical building block in the design of a transceiver for the wireless LAN (WLAN) application. The characteristic of a VCO affects the performance of the entire system of a transceiver and influences weather the system meets required specifications or not. Low phase noise and low power dissipation are important to a VCO design. Besides of these two items, the linearity of the gain of VCO (Kvco) is also an important property in the design of a VCO. The settling time is crucial to a phase-locked loop (PLL) and it will be affected by the linearity of Kvco. In the modern communication system, the quadrature signals are often used in the modulation / demodulation techniques. Among different methods for generating the quadrature local oscillating signal, the quadrature VCO (QVCO) was reported to be better with relative lower consumption and lower phase noise. The purpose of this study is to design a 5-GHz low power linearized QVCO. To achieve lower power consumption, the coupling transistors in two differential VCOs are replaced by the back-gate coupling. Besides, the circuit adopts a novel resonant circuitry with linearity technique to improve the linearity of Kvco. The resonance tank includes four p-n junction diode varactor pairs and a spiral inductor (L) for each differential VCO, and a voltage- level-shift circuitry is utilized to decide proper DC levels for each pair of varactors. The circuit was fabricated in 0.35µm TSMC SiGe BiCMOS technology under the support of Chip Implementation Center (CIC). The simulation results verify the function of the designed QVCO. The proposed QVCO has 1.5 Kvco ratio of the linearity, and operates at 5GHz band with phase noise being -116 dBc/Hz at 1MHz frequency offset. The core circuit consumes 3.46mA current at 3.0V power supply. The chip size is 0.605 x 0.745 mm2.
URI: http://hdl.handle.net/11455/8128
其他識別: U0005-1901200915554800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1901200915554800
Appears in Collections:電機工程學系所

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