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標題: 6位元1GS/s數位類比轉換器設計
Design of a 6 Bits 1GS/s Digital to Analog Converter
作者: 林佳鴻
Lin, Chia-Hung
關鍵字: DAC
D/A Converter
出版社: 電機工程學系所
引用: 1. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, Vol. 24, pp. 1433-1440, Oct. 1989 2. Jae-Jin Jung, Bong-hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim ,“A 6-bit 2.704Gbps DAC for DS-CDMA UWB,” IEEE Asia Pacific Conference Circuits and Systems, 2006. 3. Ying-Ming Laio, Tai-Cheng Lee,“A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique,” 2006 International Symposium on VLSI Design, Automation and Test. 4. Jing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer ,“A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Application,” IEEE 2006 Custom Integrated Circuit Conference (CICC) 5. Ling Yuan, Weining Ni, and Yin Shi,Foster F. Dai, Senior Member, IEEE, “A 10-bit 2GHz Current-Steering CMOS D/A Converter, ”IEEE International Symposium on Circuits and Systems 2007 6. Anne Van den Bosch, Student Member, IEEE, Marc A. F. Borremans, Student Member, IEEE,Michel S. J. Steyaert, Senior Member, IEEE, and Willy Sansen, Fellow, IEEE,“A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001 7. Kati Virtanen,Janne Maunu,Jonne PoikonenmAri Paasio,“A 12-bit Current-Steering DAC with Calibration by Combination Selection,” IEEE International Symposium on Circuits and Systems 2007 8. A. Van den Bosch,M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters,“ in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp. 1193-1196. 9. Chi-Hung Lin, K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”IEEE Journal of Solid-State Circuits,vol.33, Dec. 1998,pp. 1948-1958. 10. 朱陳糧, “10 Bits 100MS/s Digital to Analog Converter for IEEE 802.11a"國立交通大學碩士論文,中華民國九十四年九月。
摘要: 本論文設計實現一個 6 位元 1GS/s 的數位類比轉換器,此數位類比轉換器使用的是全溫度計編碼電流操縱式的架構。為了降低因為製程變異使得電流源裡的電晶體之間造成不匹配的情況,我們討論了有關電流電晶體尺寸設計,並且討論如何使 DNL 與 INL 達到小於 0.1 個 LSB 。而由梯度所引起的不匹配錯誤,透過一個四象限中心點對稱的佈局方式來消除。 使用的是 TSMC 0.35 um 的標準 CMOS 製程,供應電壓為 3.3 V , DNL ±0.1 LSB , INL ±0.3 LSB ,當輸入的時脈訊號在 10M 時,給定輸入弦波頻率 1MHz ,可得到 SFDR= 21.31dB ,功率消耗為 35.2 mW。
This thesis designs a 6-bit 1GS/s Digital-to-Analog Converter (DAC). The DAC uses full thermometer-coded current steering architecture. In order to degrade the mismatch between the transistors in the current source, we discuss about the size design of the current transistor. And we discuss how to make the DNL and INL to reach below 0.1 LSB. Gradient-induced mismatch errors are compensated by using a quadrant centro-symmetric layout. It uses TSMC 0.35 um standard CMOS technology, the supply voltage is 3.3 V. DNL is about 0.1 LSB, INL is about 0.3 LSB. When clock in = 10M, the spurious-free dynamic rang (SFDR) of 21.31 dB can be achieved with 1M digital sine input, and the total power dissipation is 35.2 mW.
其他識別: U0005-2011200823573400
Appears in Collections:電機工程學系所



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