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Voltage Control Oscillator Design For Ultra-Wideband Wireless LAN Application.
|引用:||Ian Oppermann, Matti Hämäläinen and Jari Iinatti, UWB Theory and Applications. John Wiley & Sons, Inc. 2004. S. A. Ghorashi, B. Allen, M. Ghavami and A. H. Aghvami, “An overview of MB-UWB OFDM,” Ultra Wideband Communications Technologies and System Design, pp.107-110, July 2004. D. M. W. Leenaerts,“Transceiver design for multiband OFDM UWB,” EURASIP Journal on Wireless Communacations and Networking, Article ID 43917, vol. 2006, pp.1-8,Jan 2006. B. Razavi,T. Aytur,C. Lam,F. R. Yang,K. Y. Li,R. H. Yan,H. C Kang, C. C. Hsu and C. C. Lee, “A UWB CMOS transceiver,” IEEE Journal of Solid-State Circuits, vol.40, no.12, pp.2555-2562, Dec. 2005. T. H. Lee,The Design of CMOS Radio-Frequency Integrated Circuits, New York Cambridge University Press, 1998. D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE Journal of Solid-State Circuits, vol.36, no.6, pp.896-909, June 2001. D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol.54, no.2, pp.329–330, Feb 1966. B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE Journal of Solid-State Circuits, vol. 31, no.3, pp. 329-330, March 1996. D. Hauspie,E. C. Park, J. Craninckx,B. Côme “Wideband VCO with simulataneous switching of frequency band,active core and varactor size,” IEEE Journal of Solid-State Circuits, vol.42, no.7, pp.1472-1480, Jul 2007. B. Razavi, RF Microelectronics, Prentice-Hall, 1998 K.Kurokawa,“Some basic characteristics of broadband negative resistance oscillator circuit,” Bell System Technology Journal, vol.48, pp.1937-1955 , Jul 1969 A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillator,” IEEE Journal of Solid-State Circuits, vol.34, no.5, pp.717-724, Feb 1999 A. Hajimiri, T. H. Lee, “A general theory of phase noise in electrical oscillator,” IEEE Journal of Solid-State Circuits, vol.33, no, 2, pp.179-194, Feb 1998 F. Herzel, H. Erzgraber, P. Weger, “Integrated CMOS wideband oscillator for RF applications,” IEEE Electronic Letter, vol.37, no.6, pp.330-331, Mar 2001 A. Kral, F. Behbahani, A. A. Abidi, “RF-CMOS oscillators eith switched tuning,” IEEE Custom Integrated Circuit Custom Integrated Circuits Conference, pp.555-558, May 1998 A. M. Niknejad, “Multi-mode and wideband VCO design”, RF-IC2003 Johan van Der Tang, Dieter Kasperkovitz and Arthur van Roermund, High-Frequency Oscillator Design for Integrated Transceivers, Kluwer Academic Publishers, 2003 Nathan Sneed, “A 2-GHz CMOS LC-tuned VCO using switched capacitor to compensate for bondwire inductance variation,” University of Califor- nia Berkely, Dec 2002 S. M. Sunderarajan, “Modeling ,Design and optimization of on-chip inductance and transformers”, Center for Integrated Systems,Stanford University, Jun 1999 F. Behbahani, Y. Kishigami, J. Leete and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE Journal of Solid-State Circuits, vol.36, no.6, pp.873-887, Jun 2001 K. Stadius, R. Kaunisto, V. Porra, “Monolithic tunable capacitors for RF applications,” IEEE International Symposium on Circuits and Systems, vol.1, pp.488-491, May 2001 A. Rofougaran, J. Real, M. Rofougaran and A. Abidi, “A 900 MHz CMOS LC oscillator with quadrature outputs,” IEEE International Solid-State Circuits Conference, pp.392-393, Feb 1996 M.Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE Journal of Solid-State Circuits, vol.36, no.7, pp.1018-1024, Jul 2001 H. R. Kim, C. Y. Cha, S. M. Oh, M. S. Yang and S. G. Lee, “A very low power quadrature with back-gate coupling,” IEEE Journal of Solid-State Circuits, vol.39, no.6, pp.952-955, Jun 2004 P. Andreani, A. Bonfanti, L. Romano and C. Samori, “Analysis and De- sign of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE Journal of Solid-State Circuits, vol.37, no.12, pp.1737-1747, Dec 2002 A. W. L. Ng and H. C. Luong, “A 1-V 17-GHz 5-mW CMOS quadrature VCO based on transformer coupling,” IEEE Journal of Solid-State Circuits, vol.42, no.9, pp.1933-1941, Sep 2007 A. Rofougaran, G. Chang, J. J. Rael, M. Rofougaran, P. J. Chang, M. Djafari, M. K. Ku, E. W. Roth, A. A. Abidi and H. Samueli, “A single-chip 900-MHz spread spread-spectrum wireless transceiver in 1μm CMOS —Part I：Architecture and transmitter design,” IEEE Journal of Solid-State Circuits, vol.33, no.4, pp.515-534, Apr 1998 B. J. Blalock and P. E. Allen, “A low-voltage,bulk-driven MOSFET current mirror for CMOS technology,” IEEE International Symposium on Circuits and Systems, vol.3, pp.1972-1975, 1995 Y. Zhang, P. Upadhyaya, L. Peng, D. Rector and D. Heo, “Analysis of resonator phase shift for two series LC quadrature VCOs,” Electronics Letters, vol.44, no.1, pp.26-27, Jan 2008 K. Kwok and H. C. Luong, “Ultra-Low-Voltage High-Performance CMOS VCOs using transformer feedback,” IEEE Journal of Solid-State Circuits, vol.40, no.3, pp.652-660, Mar 2005 A. Ravi, K. Soumyanath, R. E. Bishop, B. A. Bloechel and L. R. Carley, “An optimally transformer coupled,5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process,” Dig.Symp.VLSI circuits,” pp.141-144, June 2003 G. Kathiresan and C. Toumazou, “A low voltage bulk driven downcon- vesion mixer core,” IEEE International Symposium on Circuits and Systems, vol.2, pp.598-601, Jul 1999 C. Y. Jeong and C. Yoo, “5 GHz low phase noise CMOS quadrature VCO,” IEEE Mirowave and Wireless Components Letters,” vol.16, no.11, pp.609-611, Nov 2006 P. Andreani, “A 2GHz, 17% tuning range quadrature CMOS VCO with high figure-of merit and 0.6°phase error,” IEEE ESSCIRC Proceedings of the 28th, pp.815-818, Sep 2002 S. H. Lee, Y. H. Chuang, S. L. Jang, M. T. ,Chuang and R. H. Yen, “A quadrature CMOS VCO using transformer coupling and current reused topology,” IEICE transactions on communications, vol. 90, no.2, pp.346- 348 ,Feb 2007 H. Yoshizawa, K. Taniguchi and K. Nakashi, “An implementation technique of dynamic CMOS circuit applicable to asynchronous/synch- ronous logic,” IEEE International Symposium on Circuits and Systems, vol.2, pp.145-148, June 1998 D. J Yang and K. K. O, “A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to monolithic CMOS 10.4-GHz phase-locked loop,” IEEE Transaction on Microwave Theory and Techniques, vol.52, no.2, Feb 2004 M. A. Do, X. P. Yu, J.G. Ma, K.S. Yeo, R. Wu and Q. X. Zhang, “A 2GHz programmable counter with new re-loadable D flip-flop,” IEEE Conference on Electron Devices and Solid-State Circuits, pp.269-272, Dec 2003 IEEE Working Group, “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5Ghz band.,”IEEE Standard 802.11a, 1999. O. Keese. William, “An analysis and performance evaluation of a passive filter design technique for charge pump PLL’s,” National Semiconductor application note 1001, May 1996 高曜煌”射頻鎖相迴路IC設計,”滄海書局,pp.75,2005年10月。 李孟蓉,建立精準的鎖相迴路行為模型來快速分析製程漂移之影響,中央大學電機工程研究所碩士論文，2007年7月。 L. Sun and T. A. Kwansniewski, “A 1.25GHz 0.35-μm monolithic CMOS PLL based on multiphasering oscillator,” IEEE Journal of Solid-State Circuits, vol.36, no.6, pp.910-916, June 2001 J. Lee, “A 3-to-8GHz fast hopping frequency synthesizer 0.18μm CMOS technology,” IEEE Journal of Solid-State Circuits, vol.36, no.6, pp.910- 916, June 2001 W. Shen, K. Hu, X. Yi, Y. Zhou and Z. Hong, “A 5GHz CMOS monolithic fractional-N frequency synthesizer,” IEEE International Conference on ASIC, vol.2, pp.626-629, Oct 2005 B. Razavi, Design of Analog CMOS Integrated Circuits, McGRAW-HILL, 2000 J.Gibbs and R.Temple, “Frequency domain yield its data to phase locked synthesizer,” Electronics, pp.107-113, April 1978 T. Ishioka, M. Ueno, T. Nakazawa, T. Watanabe, Y. Oida and Y. Tokumaru Toshiba corporation, Semiconductor Division, “An ultra low power 500MHz dual modulus prescale”, IEEE Consumer Electronics, vol.3, pp.568-575, Aug 1985|
|摘要:||本論文以實現應用於超寬頻無線收發機內之本地振盪信號源產生電路為主；探究相關電路設計上可能遇到的問題，並實際製作出晶片加以驗證。我們使用的是國家實驗研究院晶片系統中心所提供之TSMC 0.18μm 1P6M CMOS 1.8V供應電壓製程；總共製作出兩種不同的壓控振盪器及一個完整的除整數型鎖相迴路。本論文整體將以這三塊電路為主架構，分成三個章節來講述各別之電路原理、模擬結果和最後的晶片量測結果。
This thesis mainly regards the realization of the local oscillation circuitry for the UWB wireless transceiver application. We probed into problems which may be encountered in the relevant circuit design and actually fabricated chips for verification. There are two kinds of different oscillators will be explored and we also finished one complete phase lock loop. All the chips have already been implemented in the TSMC 0.18μm 1P6M CMOS process using 1.8V supply voltage which is provided by National Chip Implementation Center (CIC). According to these three chips, this thesis also divides into three major parts. Each chapter includes principles of circuit design, simulation results and measurement results. In chapter two, we adopt discrete tuning by using switched inductors in the cross-couple pair VCO, and the tuning frequency range of the finished chip can cover UWB band 1, 2 and 3. The concept of our circuit is to combine the varactors and the switched inductors which result in two frequency bands to enlarge the tuning range of the VCO. Simulation result shows that the tuning range can reach the 2GHz (3GHz to 5GHz) requirement, and the phase noise is lower then -120dBc/Hz at 1MHz frequency offset. The measurement result shows that the best phase noise is about -108 dBc/Hz at 1MHz frequency offset when the oscillating frequency is 3.186 GHz. In chapter three, we adopt discrete tuning by using switched capacitors in the back-gated QVCO, and the tuning frequency range of the finished chip can also cover UWB band 1, 2 and 3. In order to reach higher tuning range, we just added two sets of switching capacitors in the LC tank. The characteristic of the back-gated QVCO circuit is low phase noise and low power consumption. It is shown from the simulation results that the tuning range is also from 3GHz to 5GHz. The phase noise is lower then -120dBc/Hz at 1MHz frequency offset, and the total power consumption is 10.8mW. The measurement result shows that the best phase noise is about -105.41dBc/Hz at 1MHz offset when the oscillating frequency is 4.751 GHz. In chapter four, a 802.11a low band dual-modulus phase lock loop is implement by adopting back-gate QVCO which is designed in the previous chapter. The locking frequency of the PLL is around 5.14 GHz to 5.72 GHz. The locking time is lower then 5μs, and the best peak-to-peak jitter can lower than 48.5ps.
|Appears in Collections:||電機工程學系所|
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