Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8322
標題: 應用於超寬頻無線網路之壓控振盪器設計
Voltage Control Oscillator Design For Ultra-Wideband Wireless LAN Application.
作者: 郭文福
Kuo, Wen-Fu
關鍵字: 壓控振盪器
VCO
正交壓控振盪器
鎖相迴路
QVCO
PLL
出版社: 電機工程學系所
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摘要: 本論文以實現應用於超寬頻無線收發機內之本地振盪信號源產生電路為主;探究相關電路設計上可能遇到的問題,並實際製作出晶片加以驗證。我們使用的是國家實驗研究院晶片系統中心所提供之TSMC 0.18μm 1P6M CMOS 1.8V供應電壓製程;總共製作出兩種不同的壓控振盪器及一個完整的除整數型鎖相迴路。本論文整體將以這三塊電路為主架構,分成三個章節來講述各別之電路原理、模擬結果和最後的晶片量測結果。 第二章的設計採用可切換電感方式,完成涵蓋UWB 1、2、3頻帶的互補式交叉耦合對壓控振盪器。電路概念上是搭配可變電容器並使用開關切換電感以將操作頻率分成兩個頻帶,模擬結果可調頻寬範圍在3GHz到5GHz內,相位雜訊都低於-120dBc/Hz@1MHz。最後實際量測顯示振盪在3.186GHz時有最佳相位雜訊-108dBz/Hz@1MHz。 第三章的設計則為切換電容方式之背閘極正交四相位壓控振器,同樣完成涵蓋在UWB1、2、3頻帶。為了達到高頻寬,將LC共振槽加上兩組切換電容開關,電路特點是有低相位雜訊和低功率消耗。模擬得到可調頻寬範圍在3GHz到5GHz內,其相位雜訊皆低於-120dBc/Hz@1MHz,功率消耗為10.8mW。最後實際量測顯示振盪在4.751GHz時有最佳相位雜訊-105.41dBz/Hz@1MHz。 第四章的雙模式整數型鎖相迴路設計,延用第三章部份所設計的振盪器於鎖相迴路中當作振盪源,應用在802.11a低頻帶5.15GHz到5.35GHz。而鎖定頻率在5.14 GHz到5.72GHz,鎖定時間低於5μs,最佳峰對峰抖動為48.5ps。
This thesis mainly regards the realization of the local oscillation circuitry for the UWB wireless transceiver application. We probed into problems which may be encountered in the relevant circuit design and actually fabricated chips for verification. There are two kinds of different oscillators will be explored and we also finished one complete phase lock loop. All the chips have already been implemented in the TSMC 0.18μm 1P6M CMOS process using 1.8V supply voltage which is provided by National Chip Implementation Center (CIC). According to these three chips, this thesis also divides into three major parts. Each chapter includes principles of circuit design, simulation results and measurement results. In chapter two, we adopt discrete tuning by using switched inductors in the cross-couple pair VCO, and the tuning frequency range of the finished chip can cover UWB band 1, 2 and 3. The concept of our circuit is to combine the varactors and the switched inductors which result in two frequency bands to enlarge the tuning range of the VCO. Simulation result shows that the tuning range can reach the 2GHz (3GHz to 5GHz) requirement, and the phase noise is lower then -120dBc/Hz at 1MHz frequency offset. The measurement result shows that the best phase noise is about -108 dBc/Hz at 1MHz frequency offset when the oscillating frequency is 3.186 GHz. In chapter three, we adopt discrete tuning by using switched capacitors in the back-gated QVCO, and the tuning frequency range of the finished chip can also cover UWB band 1, 2 and 3. In order to reach higher tuning range, we just added two sets of switching capacitors in the LC tank. The characteristic of the back-gated QVCO circuit is low phase noise and low power consumption. It is shown from the simulation results that the tuning range is also from 3GHz to 5GHz. The phase noise is lower then -120dBc/Hz at 1MHz frequency offset, and the total power consumption is 10.8mW. The measurement result shows that the best phase noise is about -105.41dBc/Hz at 1MHz offset when the oscillating frequency is 4.751 GHz. In chapter four, a 802.11a low band dual-modulus phase lock loop is implement by adopting back-gate QVCO which is designed in the previous chapter. The locking frequency of the PLL is around 5.14 GHz to 5.72 GHz. The locking time is lower then 5μs, and the best peak-to-peak jitter can lower than 48.5ps.
URI: http://hdl.handle.net/11455/8322
其他識別: U0005-2306200808303800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2306200808303800
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