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標題: 以二進制編碼設計之高速數位類比轉換器
High Speed Digital-to-Analog Converter Based on Binary Code
作者: 陳皇穎
Chen, Huang-Ying
關鍵字: 數位類比轉換器
current cell
出版社: 電機工程學系所
引用: [1] Jason Wibbenmeyer, Chien-In Henry Chen, “Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters,” IEEE TRANSATIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 56, NO. 6, Dec. 2007. [2] Chi-Hung Lin, K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”IEEE Journal of Solid-State Circuits,vol.33, Dec. 1998,pp. 1948-1958. [3]Jae-Jin Jung, Bong-hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim ,“A 6-bit 2.704Gbps DAC for DS-CDMA UWB,” IEEE Asia Pacific Conference Circuits and Systems, 2006. [4] Ying-Ming Laio, Tai-Cheng Lee,“A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique,” 2006 International Symposium on VLSI Design, Automation and Test. [5] Jing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer ,“A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Application,” IEEE 2006 Custom Integrated Circuit Conference (CICC) [6] Ling Yuan, Weining Ni, and Yin Shi,Foster F. Dai, Senior Member, IEEE, “A 10-bit 2GHz Current-Steering CMOS D/A Converter, ”IEEE International Symposium on Circuits and Systems 2007 [7] Anne Van den Bosch, Student Member, IEEE, Marc A. F. Borremans, Student Member, IEEE,Michel S. J. Steyaert, Senior Member, IEEE, and Willy Sansen, Fellow, IEEE,“A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001 [8] Kati Virtanen,Janne Maunu,Jonne PoikonenmAri Paasio,“A 12-bit Current-Steering DAC with Calibration by Combination Selection,” IEEE International Symposium on Circuits and Systems 2007 [9] A. Van den Bosch,M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters,“ in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp. 1193-1196. [10]M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, Vol. 24, pp. 1433-1440, Oct. 1989
摘要: 本篇論文描述高速數位類比轉換器的設計,使用的是二進制加權電流源的架構,文中提出將電流源開關的控制訊號降壓的想法,目的是為了得到較高的輸出阻抗,進而改善微分非線性誤差(DNL)以及積分非線性誤差(INL),此外,還提出一個訊號重整電路,使本電路在高速時,訊號的失真情況能受到改善,以降低突波的影響。架構中主要可分為拴鎖電路、降壓電路以及電流源單元。 模擬使用TSMC 0.18 um 標準CMOS製程,供應電壓為1.8 V,DNL
This thesis designs a high speed digital-to-analog converter (DAC). The DAC architecture uses binary-weighted current steering. In order to achieve high output impedance to improve DNL and INL, we step down the control signal of the switch on the current source. Additionally, we design a reshaping circuit to improve the distortion of signal when the circuit operates in high speed. In this way, we can reduce the effect of glitch. The architecture of the binary weighted DAC consists of a latch, a current cell, a step down circuit and a signal reshaping circuit. It is simulated by TSMC 0.18 um standard CMOS technology, the supply voltage is 1.8 V. DNL is about 0.09 LSB, INL is about 0.6 LSB. At 2 GS/s, the spurious-free dynamic rang (SFDR) of 38.9 dB can be achieved with 875 MHz, and the spurious-free dynamic rang (SFDR) of 37.3 dB can be achieved with 87.9 MHz. The power dissipation is 5.44 mW.
其他識別: U0005-2508200823442900
Appears in Collections:電機工程學系所



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