請用此 Handle URI 來引用此文件: http://hdl.handle.net/11455/8483
標題: 六位元2GHz取樣頻率二進位加權電流導向式數位/類比轉換器
A 6-bit 2-GSamples/s Binary-Weighted Current-Steering D/A Converter
作者: 吳長宇
Wu, Chang-Yu
關鍵字: DAC
數位類比轉換器
D Flip-Flop
Current Cell
暫存器
電流源
出版社: 電機工程學系所
引用: 1. Pieter Palmers, Xu Wu and Michiel Steyaert “A 130 nm CMOS 6-bit Full Nyquist 3GS/s DAC“IEEE Asian Solid-State Circuits Conference 1-4244-1360-5/07/$25.00 2007 IEEE November 12-14, 2007 / Jeju, Korea 2. Jae-Jin Jung, Bong-hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim ,“A 6-bit 2.704Gbps DAC for DS-CDMA UWB,” IEEE Asia Pacific Conference Circuits and Systems, 2006. 3. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, Vol. 24, pp. 1433-1440, Oct. 1989 4. Jae-Jin Jung, Bong-hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim ,“A 6-bit 2.704Gbps DAC for DS-CDMA UWB,” IEEE Asia Pacific Conference Circuits and Systems, 2006 5. Jae-jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim1, Sung-Mo Kang “Design of a 6 bit 1.25 GS/s DAC for WPAN” Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on 18-21 May 2008 Page(s):2262 - 2265 6. Jurgen Deveugele, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE “A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC”JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, FEBRUARY 2006 7. Chi-Hung Lin and Klaas Bult “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2“IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 8. Jing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer ,“A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Application,” IEEE 2006 Custom Integrated Circuit Conference (CICC) 9. Ling Yuan, Weining Ni, and Yin Shi,Foster F. Dai, Senior Member, IEEE, “A 10-bit 2GHz Current-Steering CMOS D/A Converter, ”IEEE International Symposium on Circuits and Systems 2007 10. Anne Van den Bosch, Student Member, IEEE, Marc A. F. Borremans, Student Member, IEEE,Michel S. J. Steyaert, Senior Member, IEEE, and Willy Sansen, Fellow, IEEE,“A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001 11. Kati Virtanen,Janne Maunu,Jonne PoikonenmAri Paasio,“A 12-bit Current-Steering DAC with Calibration by Combination Selection,” IEEE International Symposium on Circuits and Systems 2007 12. A. Van den Bosch,M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters,“ in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), Sept. 1999, pp. 1193-1196. 13. Chi-Hung Lin, K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”IEEE Journal of Solid-State Circuits,vol.33, Dec. 1998,pp. 1948-1958. 14. B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. 15. A. Van den Bosclz, M. Steyaert & W. Saizsen “SFDR-BANDWIDTH LIMITATIONS FOR HIGH SPEED HIGH RESOLUTION CURRENT STEERING CMOS DIA CONVERTERS” Volume 3, 5-8 Sept. 1999 Page(s):1193 - 1196 vol.3 Digital Object Identifier 10.1109/ICECS.1999.814383 16. 朱陳糧, “10 Bits 100MS/s Digital to Analog Converter for IEEE 802.11a"國立交通大學碩士論文,中華民國九十四年九月。 17. 林佳鴻,“6位元1GS/s數位類比轉換器設計”國立中興大學碩士論文,中華民國九十七年十月。
摘要: 本篇論文描述應用在OFDM系統上且高速、低功率消耗之數位類比轉換器的設計,其建構在二進制加權式電流源之架構上,因省略了溫度計碼解碼器之設計而使整體電路運作速度可在TSMC 180nm製程下¸達到2GS/s之取樣頻率。 晶片面積為0.25mm*0.27mm,供應電壓為1.8伏特。經過量測後其微分非線性誤差為0.11 LSB、積分非線性誤差為0.22 LSB,輸入取樣頻率為0.5GS/s時,在輸入頻率為100MHz,其動態無雜訊範圍(SFDR)為32dB,整體消耗功率約為34mW。
This paper presents the design for a 6-bit very high-speed, low-power Digital-to-Analog Converter (DAC) applied to a OFDM system. The DAC is constructed on the binary weighted current cell structure, and thus bypasses the thermometer decode design, which allows the entire circuit operation speed achieve 2GS/s under a TSMC 180nm manufacturing process. The chip area is 0.25mm *0.27 mm, and the supply voltage is 1.8 volts. The measured Differential Non-Linearity error (DNL) is 0.11 LSB, while the Integral Non-Linearity error (INL) is 0.22 LSB. When, the input sample frequency is 100MHz, the Spurious Free Dynamic Range (SFDR) is 32dB. The overall power consumption is 34mW.
URI: http://hdl.handle.net/11455/8483
其他識別: U0005-1306200913110800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1306200913110800
顯示於類別:電機工程學系所

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