Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8485
標題: 低電壓內嵌式非揮發性記憶體元件之設計
Design of Low-Voltage Embedded Non-Volatile Memory Devices
作者: 王明凱
Wang, Ming-Kai
關鍵字: Low-Voltage
低電壓
Embedded
Non-Volatile Memory Devices
內嵌式
非揮發性記憶體
出版社: 電機工程學系所
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摘要: 近年來內嵌式的記憶體架構,已被廣泛的應用在各種不同的系統上,而在密度、功率消耗以及記憶體容量上,必須不斷的提高效能。而內嵌式的記憶體系統,設計重點在於是否能跟記憶體系統以外的電路,整合在相同的製程上。如果能使用相同的製程,而又不需要增加額外的光罩,不論在設計或是製造上,都會節省相當多的時間與成本。 本論文的研究目標是參考文獻中所使用的一般CMOS製程的Single-Poly EEPROM記憶體結構與觀念,除了繼續探討此結構在不同製程下的表現,並透過設計的新型結構OTP(One Time Programming)非揮發性記憶體元件,也搭配T-CAD ISE 10.0模擬平台環境中Sentaurus Structure Editor(Sentaurus SE)這套元件結構模擬工具與HSPICE電性模擬工具等,對此元件做詳盡的介紹與動作原理分析,同時透過UMC 90nm製程的下線實作晶片及量測,運用各種MOS電晶體所設計的記憶體元件做OTP測試,以期找出適合的非揮發性記憶體操作條件。
In recent years, the embedded storage devices have been extensively applied to different systems. The density, power consumption and capacity are continually improved to enhance the performance. The key issue of embedded memory is to integrate the other circuit with the memory array in the same process technology without extra masks. That would reduce significant development time and fabrication cost. The goal of this thesis is to investigate the memory structures and design concept of well-known single-poly EEPROM using the standard CMOS technology. In addition to continuously study the performance of the same structures in different process technology, the novel OTP(One Time Programming)non-volatile memory device was designed with the assistance of the simulation tools - T-CAD ISE 10.0 Sentaurus Structure Editor(Sentaurus SE)and HSPICE. The detailed introduction and analysis of its operation principles were also presented. Using UMC 90nm technology, many memory devices with various MOS transistors were fabricated and measured in order to find the appropriate OTP non-volatile memory operation conditions.
URI: http://hdl.handle.net/11455/8485
其他識別: U0005-1307200918385100
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1307200918385100
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