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標題: CMOS環型振盪器架構之頻率合成器
Frequency Synthesizer Using A CMOS Ring Oscillator Architecture
作者: 何寬烜
Ho, Kuan-Hsuan
關鍵字: 鎖相迴路
ring oscillator
frequency synthesizer
出版社: 電機工程學系所
引用: 參考文獻 1.鎖相迴路 劉深淵、楊清淵著 滄海書局 2.類比CMOS積體電路設計 Razavi著 李泰成審校 滄海書局 3.王裕忠 “鎖相迴路系統之射頻電壓控制振盪器之研究” 國立臺灣科技大學電子工程系碩士論文 張勝良博士指導 中華民國九十四年六月 4.郭文福 “應用於超寬頻無線網路之壓控振盪器設計” 國立中興大學電機工程 研究所碩士論文 江衍忠博士指導 中華民國九十八年七月 5.Adnan Gundel ,Member, IEEE and William N. Carr , Senior Member, IEEE, “A Low Jitter CMOS PLL Clock Synthesizer with 20-400MHz Locking Range”, IEEE International Symposium on Circuits and Systems, May 2007 6.Ian A. Young,Member,IEEE, Jeffrey K. Greason, and Keng L. Wong,Member,IEEE “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.SC-27,pp. 1599-1607, November 1992
摘要: 本論文用在電子系統的頻率合成器的設計,電壓控制振盪器用環型振盪器的架構,在TSMC 0.35um 2P4M CMOS製程,可至400 MHz的工作頻率。 晶片面積是0.16mm2,功率消耗是近乎23mW。Vcontrol電壓是3.3V時,相位雜訊-95.96dBc/Hz@1MHz。振盪頻率為400MHz時,相位雜訊-95.88 dBc/Hz@1MHz。
This paper presents the design for a frequency synthesizer applied to the electronic system. The voltage controlled oscillator is ring oscillator architecture, and the circuit operation frequency achieves 400MHz based on a TSMC 0.35um 2P4M manufacturing process. The chip area is 0.16mm2.The power consumption is approximately 23mW.When the Vcontrol voltage is 3.3V, the phase noise is -95.96dBc/Hz@1MHz.When the oscillation frequency is 400MHz, the phase noise is -95.88dBc/Hz@1MHz.
其他識別: U0005-1808200911253400
Appears in Collections:電機工程學系所



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