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Design and Implementation of 90-nm Voltage Control Oscillator with Stress Relieved Topology
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第三章，考慮先進製程低壓元件薄氧化層低耐壓特性及元件安全可靠操作區間 調整VCO設計結構使兼具高振幅與高可靠度，並針對5GHz 射頻之頻段，我們使用90nm CMOS製程來實現本論文中2個VCO電路。第一個電路採用薄氧化絕緣層電晶體,頻率5.5GHz結合相位雜訊降低設計技術與減輕超壓效應架構, 第二個採用厚氧化絕緣層電晶體電路為頻率5.5GHz結合相位雜訊降低設計技術與減輕超壓效應架構。
In this thesis, the theory and implementation of LC Voltage Control Oscillator (VCOs) with stress relieved topology are studied. Firstly, a brief introduction on oscillator theory and class is described. Secondly, two behavior models are proposed to analyze the phase noise, these models explain the thermal and flicker noise contributing to the phase noise of the VCO. Based on previous knowledge of phase noise theory and over stress concerns on low voltage thin oxide device using VCO circuit, a new VCO is redesign in bias circuit to compromise both phase noise and reliability robust performances. Hence, a 90-nm CMOS technology is adopted to implement two VCO designs on 5GHz band. These two VCOs with following characteristics are designed and fabricated. Firstly, they use low phase noise architecture with identical supply voltage to implement VCO. Notably, the difference of these two VCOs is the adoption of thick oxide and thin oxide devices to generate negative resistance. The stress issue of different oxide thickness was characterized between these two VCOs. According to the experience result, the adoption of thick oxide device shows excellent performance by considering both phase noise and reliability issues. Result of this thesis provides a valuable reference during the implementation of VCO in advance technology for RF and Base-Band single chip design.
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