Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8583
標題: 針對H.264視訊標準之演算法研究及電路架構設計與實現
Algorithm and Architecture Design for H.264/AVC Video Coding Standard
作者: 陳聯霏
Chen, Lien-Fei
關鍵字: 2-D Transform Algorithm
二維轉換演算法
H.264/AVC
Intra Frame Coder
Inter Prediction
Motion Estimation
VLSI
移動估測
幀間預測
幀內畫面編碼
H.264/AVC
超大型積體電路
出版社: 電機工程學系所
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摘要: 近年來,影像以及視訊壓縮技術在多媒體資料儲存、傳輸方面變得越來越重要,此外亦越來越強調資料儲存與傳送的效率以及強健性。在本論文中,我們針對了視訊壓縮技術以及H.264/AVC視訊編碼系統之演算法與架構設計做一系列詳細的探討與研究。 二維離散餘弦轉換以及移動估測演算法在整個視訊編碼標準中佔有極為重要之角色。然而,移動估計演算法是一個非常耗時的預測編碼機制,而且其運算量佔了整體視訊編碼系統中超過一半以上。首先,我們提出了一以快速像素取樣演算法,並以此演算法為基礎提出了兩個平行移動估計架構。此具二階段處理程序之快速演算法可大幅降低絕對值相減之計算量。根據我們提出之快速演算法,第一個提出之架構利用平行運算的概念平行執行快速像素取樣演算法;第二個架構不僅支援我們提出的快速像素取樣演算法,也同時利用四平行螺旋掃描順序方法提早終止運算進一步達到降低運算的目標。 為了能夠支援各種不同的視訊標準,我們也提出了一個基於單一核心之混合型多重轉換架構用以支援各種不同類型的轉換演算法。基於新式分散式算術演算法(NEDA),我們利用遞迴離散餘弦轉換演算法降低NEDA演算法之複雜度,並提出了一個單一核心架構用以消除各種轉換所需之各類加法單元需求。由於我們提出的單一核心架構,我們只需利用兩個加法核心共十三個加法器實現二維轉換。因此,許多二為轉換係數可以利用我們的單一核心架構以及有效率的繞線網路加以實現並應用於多視訊標準之應用。 H.264/AVC是目前最新穎且最受矚目的視訊標準,而且H.264/AVC提供了顯著的編碼效率以及網路適應性。與傳統的MPEG-2、MPEG-4以及H.263相比,H.264/AVC提供了卓越了編碼效能,但是也付出了高昂的運算複雜度之代價。因此,針對H.264/AVC提出一個專用的加速架構成了當今實現視訊H.264/AVC視訊編碼器最主要的研究課題之一。針對幀間畫面預測中整數移動估計運算,我們提出了一個基於我們所提出之漸進式快速演算法之H.264/AVC整數移動估架構。首先,我們提出了一個以硬體設計為導向之漸進式快速演算法降低運算複雜度並保留了具運算規則之特性,此演算法同時具有良好之速率失真(RD:rate-distortion)表現。我們所提出之快速演算法分為兩個程序:第一個程序,又叫粗調程序,利用候選者區塊取樣(CBDS)技術以及多階層快速消除演算法(MSEA)之概念於廣大的搜尋區域中找尋數個可能具有最佳移動向量之小範圍區間;然後,第二階段(微調程序)在這些數個可能的小範圍區間執行區域全域搜尋計算最佳的移動向量。根據我們所提出之快速演算法,我們所提出之整數移動估計架構包含了記憶體模組、像素加總陣列(PSA)、具有六十四個處理單元(PE)的叢集陣列、以及SAD計算單元。此外,我們也利用記憶體插補技術有效率的安排像素資料於記憶體模組中,以便於有效率的存取像素資料。實現結果顯示,我們所設計的整數移動估測架構最高可執行每秒三十張畫面之HDTV720p解析度視訊即時編碼於60MHz的工作頻率下,此外此晶片是利用TSMC 0.18um 1P6M製程實現。 為了更進一步降低整體幀間預測之計算量,我們又提出了另外兩個快速演算法:幀間模式預決策演算法以及以泛用型高斯機率模型為基礎之移動估測提早終止機制,並加上前述提出之漸進式移動估測演算法,設計一具有功率感知之幀間預測電路架構。藉由我們所提出之幀間模式預決策演算法,最佳的幀間模式將可以在整數移動估測(IME)引擎決定,因此可大幅降低高精度移動估測(FME)引擎的運算負載。此外,我們提出了以泛用型高斯機率模型為基礎之移動估測提早終止機制用以快速的決定每個巨集區塊(MB)是否是單調或是靜態的巨集區塊,以便決定是否提早終止移動估測運算。電路實做結果顯示,我們所提出之具功率感知幀間預測架構於HDTV720p視訊即時編碼時,根據四種不同的功率感知模式僅需33 ~ 55毫瓦不等之功率消耗。 針對幀内編碼系統而言,我們也設計了一個應用於HDTV之高速高品質幀內畫面編碼器。我們所提出之幀內畫面編碼器不僅利用I4MB/I16MB資料插補排程技術,也利用我們所提出之單一核心概念所設計的多重轉換架構用以消除I4MB預測之資料相依性以及確保RD效能與H.264/AVC之JM參考軟體完全相同。
Modern video compression techniques have become more significant to employ in storing or transmitting the vast amount of data so as to represent digital video in an effi-cient and robust way. In this dissertation, the algorithm and architecture designs are discussed for the core techniques of the video compression tools and the H.264/AVC video encoding system. The two-dimensional discrete cosine transform (DCT) and the motion estimation (ME) play the key roles for the video coding standards. Two parallel motion estimation architectures are proposed based on our fast pel-subsampling algorithm. Moreover, our algorithm which is a two-stage process can reduce the computation of the absolute dif-ference. In order to fulfill a variety of the video coding standards, we also propose a hy-brid multi-transform architecture based on our unified kernel to support different kinds of the transforms. Based on the new distributed arithmetic algorithm (NEDA) and the recursive DCT algorithm, we propose the unified kernel framework to eliminate the re-quirements of different kinds of the adder cells for different coefficients. Therefore, many different 2-D transform coefficients can be easily realized via the proposed uni-fied kernel framework and the efficient routing networks to achieve the multi-standard video coding. H.264/AVC, the latest emerging and promising video standard, has improved cod-ing efficiency and the network adaptation. Compared with previous standards, it pro-vides superior coding performance at the expense of a prohibitive computational cost for real time applications. For the inter prediction, a parallel H.264/AVC integer motion estimation (IME) architecture based on our coarse-to-fine fast algorithm is proposed. In the first instance, we propose a hardware-friendly coarse-to-fine fast algorithm to reduce the computational complexity and to obtain the regular data flow with the fine rate dis-tortion (RD) performance. Our fast algorithm consists of two procedures. The first pro-cedure, called coarse step, utilizes the candidate-block down-sampling (CBDS) method and the multi-level successive elimination algorithm (MSEA) with the fixed 16x16 blockmatching search to rapidly find several possible regions within the search area. Then, the local full-search with variable block size motion estimation (VBSME) is per-formed at these possible regions at the fine step to calculate minimum SAD of the 41MVs. The corresponding IME architecture comprises the memory modules for the current block data and the reference frame pixels, the pixel sum array (PSA), the cluster array with 64 processing elements (PEs), and the SAD calculation unit. In addition, the memory interleaving technique is presented to efficiently access the search area data from the memory modules to calculate the SAD values for both of the coarse step and the fine step. The result of the chip implementation shows that the proposed architecture can accomplish the real-time video coding up to HDTV720p resolution at 60 MHz working frequency with TSMC 0.18um 1P6M process. In order to further reduce the computation of the inter prediction, another two fast algorithms, inter mode pre-decision algorithm and model-based early termination scheme of motion estimation, are also proposed and realized in our inter prediction ar-chitecture. By using the inter mode pre-decision algorithm, the best inter mode will be decided at the IME stage, and the computational loading of FME engine can be substan-tially decreased. Furthermore, we propose the model-based early termination scheme to determine whether the macroblock (MB) is homogenous or stationary to early terminate the motion estimation process of these homogenous and stationary MBs. The imple-mentation result shows the proposed power-aware inter prediction architecture con-sumes about 33 ~ 55 mW for HDTV720p applications in four different power modes. For the intra frame coding, we also propose a high-speed and high-quality intra frame coder for HDTV applications. The proposed intra frame coder not only arranges the data flow by using the interleaved I16MB/4MB data scheduling, but also utilizes the pro-posed multi-transform architectture based on our unified kernel to eliminate the data dependency of I4MB prediction and to guarantee the R-D performance of our architec-ture as good as that of JM reference software. In brief, the study of the video coding standards is contributed. The hybrid multi-transform architecture is proposed to support multi-standard video applications. Furthermore, the power aware H.264/AVC encoding system is presented with the hybrid scheduling three-stage MB pipeline, power-aware inter prediction architecture with fast algorithm, and the high-speed and high-quality baseline intra frame coder.
URI: http://hdl.handle.net/11455/8583
其他識別: U0005-1908200914403500
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-1908200914403500
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