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|標題:||IEEE 802.11n 多碼率低密度同位元查核碼解碼器之設計|
Design of IEEE 802.11n Multi-Rate LDPC Code Decoder
|引用:|| A.J. Blanksby, C.J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 404-412, March 2002.  T. Brack, F. Kienle, N. Wehn, “Disclosing the LDPC code decoder design space,” in Proc. Design, Automation and Test in Europe, March 2006, vol. 1, pp. 6.  M.M. Mansour, N.R. Shanbhag, “High-throughput LDPC decoders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 976-996, Dec. 2003.  IEEE Std 802.16e™-2005. “IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1” IEEE Std 802.16e-2005—Approved 7 December 2005; ieeexplore.ieee.org.  Europe Telecommunications Standards Institute (ETSI). “Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)” EN302 307 V1.1.2; www.dvb.org.  M.C. Davey, D. MacKay, “Low-density parity check codes over GF(q),” IEEE Communications Letters, vol. 2, no. 6, pp. 165-167, June 1998.  R. Tanner, “A recursive approach to low complexity codes” IEEE Transactions Information Theory, vol. 27, no. 5, pp. 533-547, Sep 1981.  J. Pearl, Probabilistic Reasoning in intelligent systems: networks of plausible inference. San Mateo: Morgan Kaufmann, 1988.  R.J. McEliece, D.J.C. MacKay, Jung-Fu Cheng, “Turbo decoding as an instance of Pearl''s “belief propagation” algorithm,” IEEE Journal of Selected Areas in Communications, vol. 16, no. 2, pp. 140-152, Feb. 1998.  J. L. Fan, “Constrained Coding and Soft Iterative Decoding,” Kluwer Academic Publishers, 2001  T.J. Richardson, R.L. Urbanke, “Efficient encoding of low-density parity-check codes,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 638-656, Feb 2001.  R. G. Gallager, “Low-density parity-check codes,” Cambridge, MA: MIT Press, 1963  D.J.C. MacKay, “Good error-correcting codes based on very sparse matrices” IEEE Transactions on Information Theory, vol. 45, no. 2, pp. 399-431, March 1999.  S.J. Johnson, S.R. Weller, “A family of irregular LDPC codes with low encoding complexity,” IEEE Communications Letters, vol. 7, no. 2, pp. 79-81, Feb. 2003.  F.R. Kschischang, B.J. Frey, H.-A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 498-519, Feb 2001.  IEEE P802.11n™/D9.0 “Draft STANDARD for Information Technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements; Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 5: Enhancements for Higher Throughput” IEEE P802.11n/D9.0, March 2009; ieeexplore.ieee.org.  J. Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Transactions on Information Theory, vol. 42, no. 2, pp. 429-445, March 1996.  N. Wiberg, “Codes and decoding on general graphs,” Ph.D. dissertation, Univ. Linkoping, 1996  Xiao-Yu Hu, E. Eleftheriou, D.-M. Arnold, A. Dholakia, “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” in Proc. IEEE Global Telecommunications Conference, 2001, vol. 2, pp. 1036, Nov. 2001.  M.P.C. Fossorier, M. Mihaljevic, H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Transactions on Communications, vol. 47, no. 5, pp. 673-680, May 1999.  A. Anastasopoulos, “A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution,” in Proc. IEEE Global Telecommunications Conference, 2001, vol. 2, pp. 1021-1015, Nov. 2001.  Hui-Shi Song; Ping Zhang, “Very-low-complexity decoding algorithm for low-density parity-check codes,” in Proc. Personal, Indoor and Mobile Radio Communications, 2003, vol. 1, pp. 161-165, Sept. 2003.  Jinghu Chen, M.P.C. Fossorier, “Near optimum universal belief propagation based decoding of low-density parity check codes,” IEEE Transactions on Communications, vol. 50, no. 3, pp. 406-414, March 2002.  Chugg Jun Heo, K.M., “Optimization of scaling soft information in iterative decoding via density evolution methods,” IEEE Transactions on Communications, vol. 53, no. 6, pp. 957-961, June 2005.  J. Chen, M.P.C. Fossorier, “Density evolution for two improved BP-Based decoding algorithms of LDPC codes,” IEEE Communications Letters, vol. 6, no. 5, pp. 208-210, May 2002.  M.M. Mansour, N.R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 648-698, March 2006.  J. Boutros, O. Pothier, G. Zemor, “Generalized low density (Tanner) codes,” in Proc. IEEE International Conference on Communications, vol. 1, pp. 441-445, June 1999.  O. Pothier, L. Brunel, J. Boutros, “A low complexity FEC scheme based on the intersection of interleaved block codes,” in Proc. IEEE 49th Vehicular Technology Conference, vol. 1, pp. 274-278, May 1999.  H. Behairy, S.-C. Chang, “Parallel concatenated Gallager codes,” Electronics Letters, vol. 36, no. 24, pp. 2025-2026, Nov. 2000.  H. Behairy, Shih-Chun Chang, “Parallel concatenated Gallager codes for CDMA applications,” in Proc. IEEE Global Telecommunications Conference, vol. 2, pp. 1002-1006, Nov. 2001.  H. Sankar, K.R. Narayanan, “Memory-efficient sum-product decoding of LDPC codes,” IEEE Transactions Communications, vol. 52, no. 8, pp. 1225-1230, Aug. 2004.  Jing Li; E. Kurtas, K.R. Narayanan, C.N. Georghiades, “On the performance of turbo product codes over partial response channels,” IEEE Transactions on Magnetics Part 1, vol. 37, no. 4, pp. 1932-1934, July 2001.  Jing Li; K.R. Narayanan,; C.N. Georghiades, “Generalized product accumulate codes: analysis and performance,” in Proc. IEEE Global Telecommunications Conference, vol. 2, pp. 975-979, Nov. 2001.  M.M. Mansour, N.R. Shanbhag, “Turbo decoder architectures for low-density parity-check codes,” in Proc. IEEE Global Telecommunications Conference, vol. 2, pp. 1383-1388, Nov. 2002.  M.M. Mansour, N.R. Shanbhag, “Memory-efficient turbo decoder architectures for LDPC codes,” in Proc. IEEE Workshop on Signal Processing Systems, pp. 159-164, Oct. 2002.  Zhang Juntan, M.P.C. Fossorier, “Shuffled iterative decoding,” IEEE Transactions on Communications, vol. 53, no. 2, Feb. 2005.  D.E. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proc. IEEE Workshop on Signal Processing Systems, pp. 107-112, Oct. 2004.  A. Blad, O. Gustafsson, L. Wanhammar, “An early decision decoding algorithm for LDPC codes using dynamic thresholds,” in Proc. European Conference on Circuit Theory and Design, vol. 3, pp. 285-288, Sept. 2005.  Shu-Cheng Chou, Mong-Kai Ku, Chia-Yu Lin, “Switching activity reducing layered decoding algorithm for LDPC codes,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 528-531, May 2008.  Yanni Chen, K.K. Parhi,“Overlapped message passing for quasi-cyclic low-density parity check codes,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1106-1113, June 2004.  Yongmei Dai, Zhiyuan Yan, Ning Chen;, “Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 565-578, May 2008.  Oh. Daesun, K.K. Parhi, “Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 1855-1858, May 2007.  N. Chen, Y. Dai, Z. Yan, “Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes,” in Proc. IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 220-225, Oct. 2006.  In-Cheol Park, Se-Hyeon Kang, “Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation,” in Proc. IEEE International Symposium on Circuits and Systems, vol.6, pp. 5778-5781, May 2005.  Cheng-Zhou Zhan, Xin-Yu Shih, An-Yeu Wu, “High-performance scheduling algorithm for partially parallel LDPC decoder,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 3177-3180, March 31 2008.  Tong Zhang, K.K. Parhi, “VLSI implementation-oriented (3, k)-regular low-density parity-check codes,” in Proc. IEEE Workshop on Signal Processing Systems, pp.25-36, Sept. 2001.  Xiao-Hu You, Jing Li, “Early stopping for LDPC decoding: convergence of mean magnitude (CMM),” IEEE Communications Letters, vol. 10, no. 9, pp.667-669, Sept. 2006.  F. Kienle, N. When, “Low complexity stopping criterion for LDPC code decoders,” in Proc. IEEE 61st Vehicular Technology Conference, vol. 1, pp. 606-609, June 2005.  Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu, “An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 μm CMOS Process,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 672-683, March 2008.  R.Y. Shao, Shu Lin, M.P.C. Fossorier, “Two simple stopping criteria for turbo decoding,” IEEE Transactions on Communications, vol. 47, no. 8, pp. 117-1120, Aug. 1999.  T. Brack, M. Alles, T. Lehnigk-Emden, F. Kienle, N. Wehn, N.E. L''Insalata, F. Rossi, M. Rovini, L. Fanucci, “Low Complexity LDPC Code Decoders for Next Generation Standards,” in Proc. Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, April 2007.  Yang Sun, M. Karkooti, J.R. Cavallaro, “High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems,” in Proc. IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, pp. 39-42, Oct. 2006.  Xiaonan Shi, Shingo Yoshizawa, Yoshikazu Miyanaga, “Evaluation and implementation of quasi-cyclic LDPC codes for IEEE802.11n based MIMO-OFDM system,” in Proc. IEEE Conference on Soft Computing in Industrial Applications, pp. 227-280, June 2008.  Wen Ji, Y. Abe, T. Ikenaga, S. Goto, “A high performance LDPC decoder for IEEE802.11n standard,” in Proc. Design Automation Conference, pp. 127-128, Jan. 2009.  Xing Li, Y. Abe, K. Shimizu, Zhen Qiu, T. Ikenaga, S. Goto, “Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule,” in Proc. International Symposium on Integrated Circuits, pp. 508-511, Sept. 2007.  W.A. Syafei, R. Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, Y. Nagao, B. Sai, H. Ochi, “Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n,” in Proc. IEEE Consumer Communications and Networking Conference, pp. 1-5, Jan. 2009.  Massimo Rovini, Giuseppe Gentile, Francesco Rossi, F Luca anucci, “A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes,” in Proc. IFIP International Conference on Very Large Scale Integration, pp. 236-241, Oct. 2007.  K. Gunnam, Choi Gwan, Weihuang Wang; M. Yeary, “Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 1645-1648, May 2007.  M. Karkooti, P. Radosavljevic, J.R. Cavallaro, “Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation,” in Proc. International Conference on Application-specific Systems, Architectures and Processors, pp. 360-367, Sept. 2006.  Xin-Yu Shih; Cheng-Zhou Zhan; An-Yeu Wu, “A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications,” in Proc. IEEE Asian Solid-State Circuits Conference, pp. 301-304, Nov. 2008.  W.A. Syafei, Y. Nagao, R. Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, B. Sai, H. Ochi, “Performance Evaluation of Low Density Parity Check Codes for IEEE 802.11n and Its ASIC Design,” in Proc. International Symposium on Communications and Information Technologies, pp. 609-614, Oct. 2008.  M. Rovini, G. Gentile, F. Rossi, L. Fanucci, “A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes,” in Proc. IEEE Global Telecommunications Conference, pp. 3270-3274, Nov. 2007.|
|摘要:||低密度同位元查核碼（LDPC Codes）的錯誤更正效能非常好，使得未來幾代的無線通訊系統得以實現更高的速率。本論文提出了一個高產出量、高平行度、高彈性和高擴展性的非規則低密度同位元查核碼解碼系統的硬體電路，此電路完全符合IEEE 802.11n所規範的標準：三種編碼長度648、1296和1944位元以及四種編碼速率1/2、2/3、3/4和5/6。
此多碼率低密度同位元查核碼解碼器矽智產元件實現在幾個超大型積體電路技術，包括：台積電的0.18微米和聯華電子90奈米製程，另外此架構也被實現在元件可程式化邏輯閘陣列中（XC5VLX330）。我們提出來的多碼率低密度同位元查核碼解碼器與最新的研究相比有下列的優點：（1）完全符合IEEE 802.11n的規範（20/40 MHz）；（2）大約只需要66%的面積；（3）減少22％的編碼能量消耗。|
Low-Density Parity-Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This thesis presents a high throughput, parallel, scalable and irregular LDPC decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296 and 1944 bits and coding rate 1/2, 2/3, 3/4 and 5/6 based on IEEE 802.11n standard. Our proposed LDPC decoder is a parameterize IP core running the well-known TDMP and SMSA decoding algorithm. The decoder works in pipeline, very effective technique to rearrange the sequence of its elaborations is proposed in order to minimize the iteration latency, and our proposed reducing switch activity algorithm reduces active node switching activities to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Moreover, we further improved the design with pipeline structure, parallel computation and no memory unit. Therefore, we can decode six different codewords at same time and only use one routing network to route data. The prototype architecture is being implemented on several VLSI technologies (TSMC 0.18 um and UMC 90 nm) and tested on the Xilinx Virtex-5 (XC5VLX330) FPGA. The proposed multi-rate LDPC decoder has the following advantages when compared to recent state-of-the-art architectures: (1) fully support IEEE 802.11n specification (20/40 MHz); (2) smaller normalized area about 66% in average; (3) reduced about 26% normalized energy.
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