Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8645
標題: IEEE 802.11n 多碼率低密度同位元查核碼解碼器之設計
Design of IEEE 802.11n Multi-Rate LDPC Code Decoder
作者: 黃建霖
Huang, Chien-Lin
關鍵字: LDPC
多碼率
IEEE 802.11n
Multi-Rate
decoder
低密度同位元查核碼
解碼器
出版社: 電機工程學系所
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摘要: 低密度同位元查核碼(LDPC Codes)的錯誤更正效能非常好,使得未來幾代的無線通訊系統得以實現更高的速率。本論文提出了一個高產出量、高平行度、高彈性和高擴展性的非規則低密度同位元查核碼解碼系統的硬體電路,此電路完全符合IEEE 802.11n所規範的標準:三種編碼長度648、1296和1944位元以及四種編碼速率1/2、2/3、3/4和5/6。 我們提出的低密度同位元查核碼解碼器是一個參數化的矽智產元件,可藉由一個參數就可以改變輸入輸出端的資料寬度,我們所用的解碼理論為TDMP與SMSA演算法。此解碼器的架構為管線化和我們所提出來的矩陣重排技術,同時藉由我們提出的資料交換比例降低演算法去減少節點的動態資料交換比例,來達到低密度同位元查核碼解碼器的低功率需求。減少動態資料交換比例演算法藉由分層節點的週期性更新,可以減少編碼增益的損耗。此外,我們還進一步地改進了管線化結構與平行運算單元,更重要的是我們不需要任何記憶體單元來儲存運算時的資料。因為我們的特殊設計,使得在固定的狀況下可以同時解六組編碼,而且我們只需要一組繞線網路就可以完成資料的轉送。 此多碼率低密度同位元查核碼解碼器矽智產元件實現在幾個超大型積體電路技術,包括:台積電的0.18微米和聯華電子90奈米製程,另外此架構也被實現在元件可程式化邏輯閘陣列中(XC5VLX330)。我們提出來的多碼率低密度同位元查核碼解碼器與最新的研究相比有下列的優點:(1)完全符合IEEE 802.11n的規範(20/40 MHz);(2)大約只需要66%的面積;(3)減少22%的編碼能量消耗。
Low-Density Parity-Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This thesis presents a high throughput, parallel, scalable and irregular LDPC decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296 and 1944 bits and coding rate 1/2, 2/3, 3/4 and 5/6 based on IEEE 802.11n standard. Our proposed LDPC decoder is a parameterize IP core running the well-known TDMP and SMSA decoding algorithm. The decoder works in pipeline, very effective technique to rearrange the sequence of its elaborations is proposed in order to minimize the iteration latency, and our proposed reducing switch activity algorithm reduces active node switching activities to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Moreover, we further improved the design with pipeline structure, parallel computation and no memory unit. Therefore, we can decode six different codewords at same time and only use one routing network to route data. The prototype architecture is being implemented on several VLSI technologies (TSMC 0.18 um and UMC 90 nm) and tested on the Xilinx Virtex-5 (XC5VLX330) FPGA. The proposed multi-rate LDPC decoder has the following advantages when compared to recent state-of-the-art architectures: (1) fully support IEEE 802.11n specification (20/40 MHz); (2) smaller normalized area about 66% in average; (3) reduced about 26% normalized energy.
URI: http://hdl.handle.net/11455/8645
其他識別: U0005-2507200917450600
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2507200917450600
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