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標題: 嵌入式非揮發性記憶體之高壓驅動與能隙參考電壓電路設計
Design of High Voltage Driver and Bandgap Reference Circuits for Embedded Non-volatile Memories
作者: 吳振豪
Wu, Chen-Hao
關鍵字: Embedded Non-volatile Memories
High Voltage Driver
Reference Circuits
出版社: 電機工程學系所
引用: [1]李昆鴻, ”Study of High-Qensity Embedded Single-Polysilicon Nonvolatile Memory,” 清華大學博士論文, 2005. [2]Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” VLSI Technology Symposium, Japan, pp.93-94, 2003. [3]Chia-En Huang, Hsin-Ming Chen, Han-Chao Lai, Ying-Je Chen, Ya-Chin King and Chrong Jung Lin “A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process,” IEEE International Electron Devices Meeting (IEDM), pp.91-94, 2007. [4]楊筱嵐, ”A New Logic-Compatible Differential Self-Selective Program Multiple-Time Programmable Non-Volatile Memory Cell,” 清華大學博士論文, 2009. [5]賴彌元, ”Circuits and Systems Design for Multi-level Identifying Embedded EEPROM,” 中興大學碩士論文, 2008. [6]“Quad Serial Input 12-Bit Voltage Output Digital-To-Analog Converter,” Specification, Texas Instruments Integrated Products, Sept. 2000. [7]David A. John, Ken Martin, Analog Integrated Circuit Design, Wiley. [8]K. Ohsaki and N. Asamoto, ”A Planar Type EEPROM Cell Structure by Standard CMOS Process and Applications,” IEEE VLSI Tech. Symp., pp.55-56, 1993. [9]A.O. Adan, R. Smolen, N. Tokuyama, T. Ohmi, P. Wright, R. Madurawe, A. Kagisawa, and F. Gregoire, ”A scaled 0.6um high speed PLD technology using single-poly EEPROM’s,” IEEE Custom Integrated Circuits Conference, pp.55-58, 1995. [10]Min-hwa Chi and Albert Bergemont, ”A New Single-poly Flash Memory Cell with Low-voltage and Low-power Operations for Embedded Applications,” IEEE Device Research Conference Digest, pp.126-127, 1997. [11]Anne-Johan Annema, Govert J. G. M. Geelen, and Peter C. de Jong, “5.5-V I/O in a 2.5V 0.25μm CMOS Technology,” IEEE J. Solid-State Circuits, pp. 528-538, vol.36, 2001. [12]V. Prodanov, V. Boccuzzi, “7V Tristate-capable Output Buffer Implemented in Standard 2.5V CMOS Process,” IEEE Conf. Custom Integrated Circuits, pp. 497-500, 2001. [13]Bert Serneels, Michiel Steyaert, and Wim Dehaene, “A 5.5V SOPA Line Driver in a Standard 1.2V 0.13μm CMOS Technology,” Proceedings of ESSCIRC, pp. 303-306, 2005. [14]Kwok Ping Ng, M. C. Lee, Wan Tim Chan, R. Barsatan, M. Chan, “Universal High Voltage Multiplexer for CMOS OTP Memory Applications,” IEEE Int. Conf. Electron Devices and Solid-State Circuits, pp.1-4, 2008. [15]Edward S. Yang, Microelectronic Devices, McGRAW-Hill, pp.102. [16]D. Hilbiber, “A New Semiconductor Voltage Standard,” ISSCC Dig. Tech. Papers, pp.32-33, 1964. [17]B. Razavi, Design of Analog CMOS Integrate Circuit, McGRAW-Hill, 2001. [18]K. E. Kuijk, “A Precision Reference Voltage Source,” IEEE J. Solid-State Circuits, vol. 8, pp. 222-226, 1973. [19]Eric Vittoz, and Jean Fellrath, “CMOS Analog Integrate Circuit Based on Weak Inversion Operation,” IEEE J. Solid-State Circuits, vol. sc-12 no.3, pp. 224-231, 1977. [20]G. Giustolisi, G. Palumbo, Senior, M. Criscione, and F. Cutri, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, no.1, pp.151-154, 2003. [21]V. Katyal, R. L. Geiger, D. J. Chen, “Adjustable Hysteresis CMOS Schmitt triggers,” ISCAS, pp. 1938-1941, 2008.
摘要: 本論文的研究重點可分為兩個部份,第一部分為改善用來供給內嵌式多次寫入非揮發性記憶元件位元線端之高壓驅動緩衝電路,第二部分則是提出一項新的方法,利用內嵌式非揮發性記憶元件取代傳統使用雷射燒斷電阻的方式,來達到微調能隙參考電壓電路的目的。 第一部分無可靠度問題之高電壓驅動電路是利用一般供應電壓為VDD的製程,使得電路可以達成輸出2×VDD、GND和浮接的狀態。此種高壓輸出電路主要的優點是用最少電晶體疊接的方式,讓電路在操作時電晶體各極之間的電壓不會超過VDD,且可以很容易地產生浮接的狀態,因為輸出級疊接電晶體只有兩個,每個電晶體剛好承受最大為VDD的壓差,其驅動力也較好。 至於第二部分微調能隙參考電壓電路,其電路設計的原理主要是針對先前技術中已成功實現的參考電壓電路和多次寫入非揮發性記憶體元件做整合,雖然能隙參考電壓能提供穩定輸出電壓,不會隨供應電壓源、溫度變化,然而不同晶片間仍有一些變異,搭配多次寫入非揮發性記憶體元件在寫入後,可以具有良好導通電流的特性,所以將參考電壓電路加上一適當比例的正向放大器與數個非揮發性記憶體元件,以達到參考電壓可以微調來改善精準度,而不需用雷射燒斷的傳統方式。
This thesis is focused on two circuit design issues. The first part is regarding the bit-line high voltage driver in embedded non-volatile memory systems. We effectively solved the overstress problems between each MOSFET in voltage driver circuit. In the second part, a new method has been proposed to trim the reference voltage using embedded non-volatile memory devices instead of laser cut. The first is that a high voltage driver is presented using the standard CMOS processes with supply voltage of VDD without reliability issues. The proposed circuit can generate outputs of 2VDD, GND and floating. The main features include minimizing the number of stacked MOSFETs to avoid the voltage drops between any two electrodes of a transistor higher than VDD, and making the floated output possible, which becomes a tri-state high voltge driver. Since only two transistors are stacked, the driving capability of the driver is enhanced. The second part is combining the conventional bandgap reference circuit and the special embedded non-volatile memory devices to enhance the accuracy of bandgap reference voltage. The output voltage of bandgap reference circuit is nearly constant, independent of temperatures and supply voltages. However, the reference voltage is usually fluctuated among different dies. The most popular method is using laser to trim the reference voltage. Here, the embedded non-volatile memory devices can be acted as switches. Those could be selectively programmed, so the reference voltage can be easily trimmed to the more accurate value.
其他識別: U0005-2903201013544600
Appears in Collections:電機工程學系所



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