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The RF Front-End Design Using Noise Reduction Technique for Dual Band WLAN Applications
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第二章的內容為低雜訊放大器設計。在此我們分析雜訊特性並且運用雜訊抑制的技巧設計一組雙頻帶低雜訊放大器。此電路使用TSMC 0.18 m CMOS製程製作。使用SB封裝並於PCB板量測情況底下，2.4GHz與4.7GHz量得之雜訊指數分別是4.4dB與4.6dB；功率增益則分別為9.3dB與11.2dB。此電路於1.8V偏壓下的直流功率消耗為16mW。
第三章為雙頻帶直接降頻混波器，分別使用TSMC 0.35 m SiGe BiCMOS製程及TSMC 0.18 m CMOS製程各完成一顆晶片。SiGe製程製作之晶片直接降頻至50MHz，量測結果雜訊指數20dB以下，功率轉換增益約5dB。此電路之功率轉換增益與線性度為近乎平衡的設計，以外並有良好隔離度。在3V操作電壓下，直流功率損耗為6mW。另一顆使用0.18 m CMOS製程設計之混波器亦降頻至50MHz，量得之雜訊指數約20dB，轉換增益約2dB；在1.8V操作電壓下，直流功率損耗為3.5mW。
第四章為應用於雙頻帶接收機之射頻前端電路，包含低雜訊放大器，主動巴倫電路，直接降頻混波器。此電路使用TSMC 0.18 m CMOS製程，於功率損耗25mW情況下，完成直接降頻50MHz，雙頻帶雜訊指數4dB以下，轉換增益於20dB以上，線性度高於-30dBm之模擬設計。|
This thesis presents the receiver RFIC design for WLAN 802.11a/b/g dual band application using noise reduction technique in circuit design and system conception. This thesis is composed of three parts: low noise amplifiers (LNA), mixers, and the complete receiver front end. In each part, the content includes the circuit design, system analysis, chip measurement results, and a short discussion. In chapter two, a LNA using noise reduction technique of dual band application which is implemented in TSMC 0.18 m process technology is presented. The on-bond measured NF for the proposed dual band LNA with SB package are 4.5dB and 6.8dB at frequencies 2.4GHz and 4.7GHz, respectively. The measured power gains are 9.3dB and 11.2dB at frequencies 2.4GHz and 4.7GHz, respectively. The power consumption of the proposed LNA is 16mW under 1.8V voltage supply. In chapter three, a first mixer of direct down conversion system for dual band application is implemented in TSMC 0.35 m SiGe BiCMOS process technology. The on-wafer measured NF for the mixer of the dual band system is smaller than 20dB with IF at 50MHz. The power conversion gain is near 5dB at dual band of direct down conversion system. The measured data show good isolations and balance between linearity and power conversion gain. The dc power consumption is 6mW under 3V voltage supply. On the other hand, the second mixer of direct down conversion system for dual band application is implemented in TSMC 0.18 m CMOS process technology. The on-wafer measured NF for the mixer is smaller than 20dB with IF at 50MHz. The power conversion gain is near 2dB. The mixer consumes 3.5mW power from a 1.8V voltage supply. In chapter four, a complete direct down conversion receiver RF front end for dual band application is presented. This circuit includes a dual band LNA, active balun circuits, and a direct conversion mixer, and it is designed in TSMC 0.18 m process technology. The front-end simulated NF is smaller than 4dB at dual band. The power conversion gain is more 20dB. The total power consumption is 25mW under 1.8V voltage supply.
|Appears in Collections:||電機工程學系所|
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