Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8922
標題: 8 bit逐漸逼近式類比數位轉換器使用Binary Switch Array 電容結構
An 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique
作者: 黃郁偉
Huang, Yu-Wei
關鍵字: Successive Approximation ADC
逐漸逼近式類比數位轉換器
出版社: 電機工程學系所
引用: [1] K.B. Ohri, M.J. Callahan ,“Integrated PCM codec ,”IEEE Journal of Solid-State Circuits, vol. 14,no. 1,pp. 38 - 46 ,FEBRUARY 1979. [2]Guang-Kaai Dehng , June-Ming Hsu , Ching-Yuan Yang , Shen-Iuan Liu , “Clock-deskew buffer using a SAR-controlled delay-locked loop ,” IEEE Journal of Solid-State Circuits, vol. 35,no. 8,pp. 1128 - 1136, Aug. 2000. [3]Seung-Chan Heo,Young-Chan Jang, Sang-Hune Park, Hong-June Park,“An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique ,” IEEE International ASIC/SOC Conferences, pp.80 - 83, Sept. 2002. [4]Kwangho Yoon, Jeongho Lee, Deog-Kyoon Jeong, Wonchan Kim,“An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI ,”Symposium on VLSI Circuits Digest of Technical Papers, pp. 212 - 213, June 2000. [5]Samgsuk Kim, Minkyu Song, “An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver,” IEEE International Symposium on Circuits and Systems, vol. 1,pp. 528 - 531, May 2001. [6] A.M. Abo , P.R. Gray ,“A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,”IEEE Journal of Solid-State Circuits, vol. 34, no. 5,pp. 599 - 606 , MAY 1999. [7] A. Agnes, E. Bonizzoni, P. Malcovati, F. Maloberti ,“A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator,” IEEE International Solid-State Circuits Conference Digest of Technical Papers , Feb. 2008. [8] B.P. Ginsburg , A.P. Chandrakasan ,“500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,”IEEE Journal of Solid-State Circuits, vol. 42, no. 4,pp. 739 - 747 , APRIL 2007. [9] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, “A 1.9W4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2008. [10]J. Sauerbrey, D. Schmitt-Landsiedel, R. Thewes, “A 0.5-V 1-μW successive approximation ADC ,” IEEE Journal of Solid-State Circuits, vol. 38,no. 7, pp. 1261 - 1265, July 2003. [11]Behzad Razavi 著,李泰成 審校, “類比CMOS積體電路設計,” 滄海書局,2005。 [12]NEIL H.E. WESTE ,DAVID HARRIS 著, 柯鴻禧,黃琪聰 譯, “CMOS積體電路設計概論,”高立圖書有限公司,中華民國九十六年十二月。 [13]李博明,唐經洲,“VLSI設計概論/實論,” 高立圖書有限公司,中華民國九十四年七月。 [14]吳長宇,“六位元2GHz取樣頻率二進位加權電流導向式數位/類比轉換器,” 國立中興大學碩士論文,中華民國九十八年六月。 [15]林建彰,“8 bits逐步逼近式類比數位轉換器,” 國立中興大學碩士論文,中華民國九十八年七月。 [16]范綱瑾,“應用同步比較實現3.3伏特8位元250MHz取樣頻率14毫瓦特之電流模式類比數位轉換器,” 國立中山大學電機工程學系碩士論文,中華民國九十四年六月。
摘要: 本篇論文描述一個類比數位轉換器的設計,使用的結構是Binary Switch Array電容之8 bit逐漸逼近式類比數位轉換器架構,在TSMC 0.35μm Mixed-Signal 2P4M Polycide 3.3V製程下,達到1M Sample/s之取樣頻率。 第一顆SAR-ADC之晶片面積為1925μm×1579μm,供應電壓為3.3伏特。當時脈訊號頻率(Clock)為1MHz ,取樣頻率(Sample Rate)為100KHz,輸入Sin弦波頻率為10KHz(振幅為0V~2.4V)時之量測結果如下: 其微分非線性誤差(DNL)為-1LSB ~ 72.986LSB、積分非線性誤差(INL)為-86.961LSB ~ 25.296LSB、SNDR=14.05dB與ENOB=2.04bits,整體消耗功率約為3.287mW。 第二顆SAR-ADC之晶片面積為1295μm×1120μm,供應電壓為3.3伏特。當時脈訊號頻率(Clock)為1MHz ,取樣頻率(Sample Rate)為100KHz,輸入Sin弦波頻率為10KHz(振幅為0V~2.4V)時之量測結果如下: 其微分非線性誤差(DNL)為-1LSB ~ 9.132LSB 、積分非線性誤差(INL)為-7.364LSB ~ 20.255LSB、SNDR=27.5dB與ENOB=4.28bits,整體消耗功率約為2.566mW。
This thesis designs an analog-to-digital converter (ADC). The architecture is an 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique , and the sample rate of the circuit achieves 1MSample/s based on a TSMC 0.35μm Mixed-Signal 2P4M Polycide 3.3V manufacturing process. The Chip area of the first SAR-ADC is 1925μm×1579μm , and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz , sample rate is 100KHz , and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V): Its Differential Non-Linearity error (DNL) is -1LSB~72.986LSB, Integral Non-Linearity error (INL) is -86.961LSB ~ 25.296LSB , SNDR=14.05dB , ENOB=2.04bits , and the whole power consumption is approximately 3.287mW. The chip area of the second SAR-ADC is 1295μm×1120μm , and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz , sample rate is 100KHz , and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V): Its Differential Non-Linearity error (DNL) is -1LSB ~ 9.132LSB, Integral Non-Linearity error (INL) is -7.364LSB ~ 20.255LSB , SNDR=27.5dB , ENOB=4.28bits , and the whole power consumption is approximately 2.566mW.
URI: http://hdl.handle.net/11455/8922
其他識別: U0005-2308201014560500
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2308201014560500
Appears in Collections:電機工程學系所

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