Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8954
標題: 先進奈米級CMOS元件之模擬與研究
A TCAD Simulation Study for Advanced Nanoscale CMOS Devices
作者: 王維敬
Wang, Wei-Ching
關鍵字: subband
次能帶
effective mass
mobility
strained Si
1-D analytical model
有效質量
遷移率
應變矽
一維分析模型
出版社: 電機工程學系所
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Zawadzki, &quot;A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging.&quot; in IEDM Tech. Dig., pp. 247-250, 2007.
摘要: 在本篇論文之中,作者首先探討應變CMOS對次能帶結構與遷移率的影響。對一受[110]單軸應力之N型金氧半場效電晶體而言,作者使用k.p方法來計算其次能帶結構與有效質量的改變,進而與實驗數據來比對其遷移率的變化,然可從中發現其與通道方向的函數關係;而對一受雙軸應力之P型金氧半場效電晶體而言,探討其在不同應力條件下,反轉層電洞的有效質量之變化,係包涵量子化有效質量(quantization effective mass, mz)、狀態密度有效質量(density of state effective mass, mDOS)和電導率質量(conductivity mass, mσ)等。 其次探討通道寬度對具有矽鍺或矽碳合金應力源(S/D stressor)及CESL(SiN覆蓋層)之N或P型MOSFET通道內應力場的分佈之影響。以NMOS來說,分析發現金氧半場效電晶體寬度在寬的width時,沿傳輸方向的Sxx應力主導整個遷移率增益;沿寬度方向的應力對電流影響不大;而沿垂直方向的壓縮應力對遷移率增益有其影響性,不可以被忽略。在width小的時候,Szz的應力會減少,造成遷移率的增益降低。此外,作者也分析寬度對電流增益提升的關係。以PMOS來說,分析發現電晶體寬度在寬的width時,沿傳輸方向的Sxx應力主導整個遷移率增益;沿寬度方向的應力對電流影響不大;而沿垂直方向的壓縮應力對遷移率增益幾乎沒影響,可以被忽略,此與NMOS大大不同。在width小的時候,Sxx的應力會減少,造成遷移率的增益降低。此外,作者也分析不同寬度下對電流增益提升的關係。 最後,作者推導一個簡單的一維分析模型,並藉由與三維模擬結果的比較,可以幫助使用者在短閘極長度及大閘極寬度下,快速地估測一受矽鍺或矽碳影響之電晶體通道應力值。
In this dissertation, an effect of subband structure and mobility for CMOS was firstly studied. For an NMOS used by uniaxial stress, the author was interested an effect of stress distortion on the conduction band structure derived by k.p method. From k.p conduction band calculations, stress-induced band edge split and the change of effective mass were quantitatively evaluated. So that the variation of experimental electron mobility in the silicon n-channel metal-oxide-semiconductor field-effect-transistors under a [110] uniaxial stress as a function of channel direction could be theoretically studied. For an PMOS used by biaxial stress, the hole subband structures in inversion layers of strained Silicon (Si) transistors under different strain conditions were studied theoretically. Various effective masses of hole inversion layers used in technology computer-aided design (TCAD) simulations were investigated, such as the quantization effective mass, mz, the density of states effective mass, mDOS, and the conductivity mass, mσ. Next, the stress distributions in the Si channel regions of silicon-based alloy source/drain and stressed silicon nitride liner NMOSFETs with various widths were studied using 3D TCAD simulations. For strained Si NMOS, drive current enhancement was found to be dominated by tensile stress along the transport direction (Sxx) and compressive stress along the growth direction (Szz) in larger width devices. Stress along the width (Syy) was found to have the least effect on the drain current in the large width regime. The compressive stress along the vertical direction, perpendicular to the gate oxide (Szz), contributed significantly to drive current enhancement and could not be neglected in NMOSFETs. For strained Si PMOS, it was found that Sxx contributed most substantially to the improvement in drive current, while Szz contributed the least. In the narrow width regime Syy noticeably enhanced drive current and contributed almost a quarter of the total gain. Last, a simple 1-D analytical model was considered and compared with the 3-D simulation result. The analytical model could help users to easily estimate Si1−xGex and Si1−yCy S/D stress in nested transistors.
URI: http://hdl.handle.net/11455/8954
其他識別: U0005-2608201015035000
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