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Local Oscillation Signal Generation Circuit Design for Dual Band Applications
|引用:||H.L. Kao, D.Y. Yang, A. Chin, and S.P. McAlister, “A 2.4/5 GHz Dual-Band VCO using a Variable Inductor and Switched Resonator,” IEEE Conferences of Microwave Symposium, pp.1533-1536, June 2007. K. Kurokawa, J.P. Beccone, and N.D. Kenyon, “Broadband Negative Resistance Oscillator Circuits,” IEEE Conferences of Microwave Symposium, pp.281-284, May 1969. Lin Jia, Jian-Guo Ma, Kiat Seng Yeo, and Manh Anh Do “A novel methodology for the design of LC tank VCO with low phase noise,” IEEE Conferences of Circuits and Systems, Vol.1, pp.376-379, May 2005. Byunghoo Jung, and R. Harjani, “A wide tuning range VCO using capacitive source degeneration,” IEEE Conferences of Circuits and Systems, Vol.4, pp. IV 145-148, May 2004. K. Yamamoto, T. Norimatsu, and M. Fujishima, “High-speed and wide-tuning-range LC frequency dividers,” IEEE Conferences of Circuits and Systems, Vol.4, pp.IV 361-364, May 2004. Hui Wu, and Lin Zhang, “A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider,“ IEEE Conferences of Solid-State Circuits, pp.2482-2491, February 2006. R. Aparicio, and A. Hajimiri, “A Noise-Shifting Differential Colpitts VCO,” IEEE Journal of Solid-State Circuits, Vol.37, pp.1728-1736, December 2002. A.L. Lacaita, and C. Samori, “Phase-noise performance of crystal-like LC tanks,“ IEEE Journal of Circuits and Systems, Vol.45, pp.898-900, July 1998. K. Kugimiya, G. Fuse, S. Akiyama, and A. Nishikawa, “101-Stage 2 µm gate ring oscillators in laser-grown silicon islands embedded in SiO2,” IEEE Journal of Electron Device Letters, Vol.3, pp.270-272, September 1982. D. Ham, and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE Journal of Solid-State Circuits, Vol.36, pp.896 -909, June 2001. Zhenbiao Li, and K.K O, “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE Journal of Solid-State Circuits, Vol.40, pp.1296-1302, June 2005. P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,“ IEEE Journal of Solid-State Circuits, Vol.37, pp.1737-1747, December 2002. D.B Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” IEEE Journal of Proceedings, Vol.54, pp.329-330, February 1966. Jong-Phil Hong, Seok-Ju Yun, Nam-Jin Oh, Sang-Gug Lee, “A 2.2-mW Backgate Coupled LC Quadrature VCO With Current Reused Structure,”IEEE Journal of Microwave and Wireless Components Letters, Vol.17, pp.298-300, April 2007. Nam-Jin Oh, and Sang-Gug Lee, “Current reused LC VCOs,” IEEE Journal of Microwave and Wireless Components Letters, Vol.15, pp.736-738, November 2005. Behzad Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal of Solid-State Circuits, Vol.39, pp.1415-1424, September 2004. M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE Journal of Solid-State Circuits, Vol.39, pp.1170-1174, July 2004. H.R. Rategh, and T.H. Lee, “Superharmonic Injection-Locked Frequency Dividers,” IEEE Journal of Solid-State Circuits, Vol.34, pp.813-821, June 1999. S. Verma, H.R. Rategh, and T.H. Lee, ”A unified model for injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, Vol.38, pp.1015-1027, June 2003. Sheng-Lyang Jang, Chien-Feng Lee, and Wei-Hsung Yen, “A Divide-by-3 Injection Locked Frequency Divider With Single-Ended Input,” IEEE Journal of Microwave and Wireless Components Letters, Vol.18, pp.142-144, February 2008. A. Hajimiri, and T.H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, Vol.33, pp.179-194, February 1998. Ping-Yuan Deng, and Jean-Fu Kiang, “A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors,” IEEE Journal of Circuits and Systems, Vol.56, pp.320-326, February 2009. 詹爵安, “應用於雙頻帶無線區域網路之射頻前端電路設計,” 國立中興大學電機工程學系碩士學位論文, July 2009. 吳明峰, “本地振盪信號源產生電路設計,” 國立中興大學電機工程學系碩士學位論文, July 2009. 王銓慶, “應用於MB-OFDM Model-1 UWB 接收機之CMOS壓控振盪器與頻率合成器的研製,” 國立成功大學電腦與通信工程研究所碩士論文, July 2007. 郭文福, “應用於超寬頻無線網路之壓控振盪器設計,” 國立中興大學電機工程學系碩士學位論文, July 2008. Simon Haykin, 翁萬德, 江松茶 譯, “通訊系統4th,” 全華科技,2001. Floyd M. Gardner 著, 姚劍清 譯,” 鎖相環技術3th,” 人民郵電, 2007. A. Aktas, and M. Ismail, “CMOS PLL ands VCOs for 4G Wireless,” Kluwer Academic 2004. Behzad Razavi, “RF Microelectronics,” Prentice-Hall, 1998. Behzad Razavi, “Design of analog CMOS integrated circuits,” McGraw Hill, 2001. Behzad Razavi, “Design of integrated circuits for optical communications, ” McGraw Hill, 2003. 劉深淵, 楊清淵, “鎖相迴路,” 滄海書局, 2008. D-Link技術團隊, “無線區域網路技術白皮書,” 松崗, 2005.|
第二章主要設計一個電流再利用架構之背閘極正交訊號壓控振盪器。電路設計概念上主要利用三個技巧：第一是電流再利用架構，第二為背閘極耦合技術，第三是使用源極退化電容架構。使用這些技巧可以使電路達成低功率損耗、低相位雜訊、降低共振器寄生容值等優點。晶片使用TSMC 0.35μm BiCMOS製程製作。量測時在供應電壓3.3V下直流功耗為10.56mW；可調頻寬為3.43-4.04GHz，當振盪於3.82GHz頻率時量得之相位雜訊為-117.71dBc/Hz@1MHz frequency offset。
第三章主要設計一個電感電容共振器注入鎖定除三除頻電路。電路架構由注入鎖定除二電路、降頻式混波器所組成。電路主要是除二電路與混波器疊接，藉由電流共用所以可節省功耗。晶片使用TSMC 0.18μm CMOS製程製作。量測時在供應電壓1.8V下直流功耗為23.4mW；當輸入訊號功率為0dBm時，量得之可鎖定頻率範圍為3.26-4.37GHz。
第四章主要設計頻率合成器電路。第一顆晶片為除單整數480頻率合成器，模擬鎖住頻率在3.84GHz，晶片使用TSMC 0.18μm CMOS製程製作，量測時在供應電壓1.8V下直流功耗為21.3mW，結果並未鎖住。第二顆晶片為可程式雙模除整數除頻器，改良自前一顆晶片，模擬時在供應電壓1.8V下直流功耗為9.98mW，操作頻率為3.61-4.41GHz。|
In this thesis, we realize the local oscillation signal generation circuit design for dual band applications. The dual-band architecture for generating the local oscillation signal is composed of a signal source, a divide-by-3 frequency divider and a down/up conversion mixer. The contents of this thesis can be divided into three main chapters as described following, including circuit design concepts, simulation results, and final measurements of chips. In chapter two, a quadrature VCO using back-gate coupling technique and serial LC tank with current reuse structure is presented. In this proposed VCO, three important techniques are adopted: first, the current-reuse architecture, second, the back-gate coupling technique, and third, the source degeneration capacitor technique. With help of these novel methods, the VCO can achieve low power consumption, low phase noise, and low parasitic capacitance. The chip is fabricated using the TSMC 0.35μm BiCMOS process technology. The measured power consumption is 10.56mW under 3.3V dc supply voltage. The measured tuning range is 3.43-4.04 GHz, and the measured phase noise is -117.71 @ 1MHz frequency offset with a 3.82GHz oscillating frequency. In chapter three, a divide-by-3 LC tank based injection-locked frequency divider is presented. It is composed of two injection-locked divide-by-2 circuits and a single sideband down conversion mixer. In order to save the power consumption, the divide-by-2 circuits are cascaded above the mixer circuit and therefore the current can be shared. This chip is fabricated using the TSMC 0.18μm CMOS process technology. The measured power consumption is 23.4mW under 1.8V dc supply voltage. The Operation range of this chip is around 3.26 to 4.37GHz when the input signal is at 0dBm power level. In chapter four, designs of frequency synthesizers are presented. The first chip is a frequency synthesizer that adopted the divide-by-480 integer-N architecture. The output frequency can be locked at 3.84GHz under simulation. The chip is fabricated using the TSMC 0.18μm CMOS process technology. The measured power consumption is 21.3mW under 1.8V dc supply voltage. And the results show that it cannot lock as simulation. The second chip is a dual-modulus frequency synthesizer and it is modified from the previous one. The simulated power consumption is 19.98mW under 1.8V supply voltage. And the simulated Operating frequency of this chip is around 3.61 to 4.41GHz.
|Appears in Collections:||電機工程學系所|
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