Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9020
標題: 2.4GHz全數位頻率合成器
2.4GHz All Digital Frequency Synthesizer
作者: 呂淙安
Lu, Cong-An
關鍵字: 鎖相迴路
phase locked loop
全數位鎖相迴路
頻率合成器
全數位頻率合成器
all digital phase plocked loop
frequency synthesizer
all digital frequency synthesizer
出版社: 電機工程學系所
引用: [1]劉深淵、楊清淵,鎖相迴路,滄海書局,2006 [2]陳世璋, “使用雙延遲鎖相迴路自我校證的游標尺時間至數位轉換 器”,國立中興大學電機工程研究所論文,2008 [3]楊松諭,”一個10GHz快速鎖定之全數位頻率合成器”,國立交通大學電子研究所論文,2008 [4]古識涵,”具有自我迴路頻寬校正之全數位展頻時脈產生器與解展頻時脈產生器”,國立台灣大學電機資訊學院電子工程學研究所碩士論文, 2012 [5]盧泓諭,”一個使用嵌入式有限脈波響應濾波器的60億赫茲除小數頻率合成器”,國立台灣大學電機資訊學院電子工程學研究所碩士論文, 2011 [6]邱威豪,”快速鎖定與低雜訊之鎖相迴路設計”國立台灣大學電子工程學研究所,2011 [7]B. Razavi, Design of Analog CMOS Integrated Circuit, MA: McGraw -Hill, 2001. [8]B. Razavi, Design of Integrated Circuits for Optical Communications. Boston: McGraw-Hill,2003. [9]T. Riley, M. Copeland, and T. Kwasniewski, Delta-sigma modulation in fractional-N frequency synthesis, IEEE Journal of Solid-State Circuits, vol. 28,no. 5,pp. 553- 559 ,May 1993. [10]Kratyuk. V., Corvallis. OR, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy”, IEEE Trans. Cir-cuits Sys. II, Exp. Briefs, vol.54, Issue3, pp.247-251,March 2007 [11]R.B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, Wiley-Interscience, 2006 [12]M.Z. Straayer, "Noise Shaping Techniques for Analog and Time to Digital Converters Using Voltage Controlled Oscilllators," PhD Thesis, MIT, June 2008. [13]Stephan Henzler, 2010, “Time-to-Digital Converters” [14]P.Dudek, S. Szczepanski and J.V. Hatfield, “A High-Resolution CMOS Time-to- Digital Converter Utilizing a Vernier Delay Line,”IEEE J. Solid-State Circuits, vol.35, no.2, pp240-247, Feb. 2000 [15]A. H. Chan and G. W. Roberts, “A Jitter Characteristization System Using a Component-Invariant Vernier Delay Line,”IEEE Transactions on Very Large Scale Integration(VLSI) Systems, vol.12, no.1, pp. 79-95, Jan. 2004 [16]Sheng-You Lin and Shen-Iuan Liu, “A 1.5GHz All-Digital Spread-Spectrum Generator”, IEEE J. Solid-State Circuits, vol.44, no.11, pp.3111-3119, Nov. 2009 [17]Abdel S. Yousif and James W. Haslett, “A Fine Resolution TDC Architecture for Next Generation PET Imaging”IEEE Trans. Nucl. Sci., vol.54., no.5 ,pp1574-1582, Oct., 2007 [18]V. Ramakrishnan, Poras T. Balsara, “A Wide-Range, High-Resolution, Compact, CMOS Time to Digital Converter”,in Proc. VLSI Design(VLSID`06), pp.197-202 , Jan. 2006 [19]Tokairin, T. , Okada, M , “A 2.1-to-2.8GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter”IEEE J. Solid-State Circuits, vol.45, No.12, pp2582-2590, Dec., 2010 [20]X.F. Kuang and N.J. Wu, “A Fast-settling PLL frequency synthesizer with direct frequency presetting,”ISSCC Dig. Tech. Papers, pp.741-742, Feb.2006. [21]C.-Y. Yang and S.-I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,”IEEE J. Solid-State Circuits, vol. 35, pp.1445-1452, Oct. 2000. [22]Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin, “A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops”, IEEE J. Solid-State Circuits, vol. 45, no.6, pp.1137-1149 , June, 2010 [23]Song-Yu Yang, Wei-Zen Chen, “A 7.1mW 10GHz All Digital Frequency Synthesizer with dynamically Reconfigured Digital Loop Filter in 90nm CMOS Technology”, ISSCC Dig. Tech. Papers, pp. 90-91, Feb. 2009 [24]Xin Chen, Jun Yang, Long-Xing Shi, “A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique”, IEEE Trans. Very Large Scale Integr.(VLSI) Syst. Vol.19, no.5, pp.857-868, May,2011 [25]V. Kratyuk, P.K. Hanumolu, U.-K. Moon and K. Mayaram, “Frequency detector for fast frequency lock of digital PLLs”, Electronics Letters, vol. 43, no. 1, Jan., 2007 [26]I. A. Young, J. K. Greason and K. L. Wong, “A PLL clock generator with 5 to 110MHz of lock range for microprocessors”, IEEE J. Solid-State Circuits, vol.27, pp.1599-1607,Nov. 1992 [27]Jen-Chieh Liu, Hong-Yi Huang, “0.5V 160MHz 260uW All-Digital Phase-Locked Loop ”DDECS, April. 2009, pp.186-193 [28]Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh, “All Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithm”,in: International Symposium on Circuits and Systems(ISCAS), May 2011,pp.486-489 [29]Robert Bogdan Staszewski, “State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 7, pp.1497-1510, July, 2011 [30]Chun-Ming Hsu, Straayer, M.Z., Perrott, M.H., “A Low-Noise, Wide-BW 3.6GHz Digital ∆Σ Fractional-N Frequency Synthesizer with a Noise-Shapping Time-to-Digital Converter and Quantization Noise Cancellation” IEEE J. Solid-State Circuits, vol. 58, no.7, pp.2776-2786, Dec., 2008 [31]Liangge Xu, Kari Stadius, “An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique. ”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no.11 , pp.2481-2494, Nov.,2012 [32]Wei Liu, Wei Li, “A PVT Tolerant 10 to 500MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO”, IEEE J. Solid -State Circuits, vol. 45, no.2, pp.314-321, Feb.,2010 [33]Takashi Tokairin, Mitsuji Okada, “A 2.1-to-2.8GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time -to - Digital Converter” [34] C.-C. Chung and C.-Y. Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE J. Solid-State Circuits, vol. 38, pp. 347-351, Feb.2003. [35]Sheng-You Lin and Shen-Iuan Liu,“A 1.5 GHz All-Digital Spread-Spectrum Clock Generator”IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009. [36]T.-C. Huang, et. al., “All digital phase-locked loop using active inductor oscillator and novel locking algorithm,” Int. Sym. Circuits Syst. (ISCAS), May 2011, pp.486-489. [37]Liangge Xu; Lindfors, S.; "A 2.4-GHz Low-Power All-Digital Phase-Locked Loop" , JSSC , vol.45 , p.1513 , 2010 [38]M. A. Ferriss and M. P. Flynn, “A 14 mW fractional-N PLL modulator with a digital phase detector and frequency switching scheme,” IEEE J. Solid-State Circuits, vol. 43, pp. 2464–2471, Nov. 2008.
摘要: 在目前的無線通訊中,我們一直希望無線收發機能夠在很寬廣的頻率範圍下切換頻率。因此,為了能夠在每一個通訊系統的通道產生所需的載波,一個穩定且可任意切換頻率的頻率合成器是必須的。其中一個在CMOS技術製程底下實現頻率合成的方法為建置全數位頻率合成器。全數位的實現方式可以對製程、電壓、溫度變異以及基底雜訊有較高的容忍度。同時,全數位頻率合成器具有以下的優點,像是較小的佈局面積、較容易驗證的特性、較低的功率消耗。這篇論文主要的內容是在設計應用於ISM頻帶的CMOS射頻全數位整數型頻率合成器。 本篇論文介紹了數種的時間數位轉換器架構以及具有快速鎖定技巧的全數位鎖相迴路,並實現三個具有快速鎖定技巧的全數位頻率合成器。第一個架構主要是具有鎖頻迴路以及鎖相迴路的頻率合成器,其鎖頻迴路可以偵測頻率差,加快鎖定的時間,其製程是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.2mm ×1.19964 mm,輸出鎖定範圍為2.02GHz-2.25GHz,鎖相迴路的相位雜訊為-97.97dBc/ Hz,在操作電壓為1.8V下,消耗功率為75mW,鎖定時間最快為76us。第二個架構為具有鎖頻迴路以及相位差補償技巧電路的全數位頻率合成器,相位差補償技巧電路可以改善相位差快速累積的問題,因此能夠達到更快速的鎖定,其製程是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.4mm ×1.4mm,模擬結果的輸出鎖定範圍為2.08GHz-2.403GHz,鎖相迴路的相位雜訊為-108dBc/Hz,在操作電壓為1.8V下,消耗功率為50mW,鎖定時間最快為45us。第三個架構為具有三段時間數位轉換器和相位差補償技巧的全數位頻率合成器,時間數位轉換器能達到寬範圍且高解析度,其製程亦是使用台積電0.18微米互補式金氧半導體製程,晶片面積為1.2mm×1.196mm,其模擬結果輸出鎖定範圍為2.325GHz-2.485GHz,鎖相迴路的相位雜訊為-120 dBc/Hz,在操作電壓為1.8V下,消耗功率為55mW,鎖定時間最快為6us。
In modern wireless communication, transceivers are expected to switch over a wide range of frequencies. Hence , a stable and switchable frequency synthesizer is employed to generate the required carriers for each channel in communication system. One approach to realize frequency synthesis is to implement an all-digital frequency synthesizer in CMOS technology. All digital approach can have a high tolerance to against process-voltage-temperature (PVT) variation and substrate noise . It also have many advantages, including smaller layout area, ease of testability, and less power dissipation. In this thesis, a CMOS RF all digital integer-N frequency synthesizer for ISM band is designed. The thesis introduces several time-to-digital converters and all-digital phase-locked-loops with fast locking techniques. The first topology is a dual-loop all digital frequency synthesizer with frequency locked loop (FLL) and phase locked loop. The FLL detects the frequency error, and it also speeds up locking time.It is fabricated in TSMC 0.18um CMOS process, and it can provide the output frequency locking range from 2.01 GHz to 2.25GHz. The phase noise of the all digital frequency synthesizer is -97.97dBc/Hz. When the output locking frequency is 2.25GHz, the locking time is 76us and the power dissipation is 75mW under 1.8V supply voltage. The second topology is a dual-loop all digital frequency synthesizer with frequency-locked-loop and phase error compensation technique . The phase error compensation technique can improve large phase error accumulation problem. Fabricated in TSMC0.18um process, it can provide the output frequency locking range from 2.08GHzGHz to 2.403GHzGHz. When the output locking frequency is 2.402GHz, the locking time is 45us us and the power dissipation is 50mW under 1.8V supply voltage. The third topology is an all digital frequency synthesizer with phase error compensation technique and three time-to-digital converters.The time-to-digital converter can achieves wide range and high resolution performance . Fabricated in TSMC0.18um process, it can provide the output frequency locking range from 2.325GHz to 2.485GHz. When the output locking frequency is 2.405GHz, the locking time is 6us and the power dissipation is 50mW under 1.8V supply voltage.
URI: http://hdl.handle.net/11455/9020
其他識別: U0005-2008201312093000
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2008201312093000
Appears in Collections:電機工程學系所

文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.