Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9067
標題: 以SystemC建模及架構分析之調頻連續波雷達基頻處理器設計與可程式邏輯閘陣列上之實現
SystemC based modeling and architectural analysis of an FMCW radar baseband processor and its FPGA implementation
作者: 陳奕志
Chen, Yi-Jr
關鍵字: 調頻連續波雷達
FMCW radar
電子系統層級設計
ESL design
SystemC
出版社: 電機工程學系所
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[7] 湯朝景,「應用於頻率調變連續波雷達系統的類比數位轉換器」,雲林科技大學通訊工程研究所碩士論文,民國98年 [8] Robert C. Chen, Alan P. Su "Construct A PAC PMP SoC Verification Platform Using ESL Design Methodology,"SoC Technical Journal, No.4, pp. 66-77, 2006 [9] 陳紀綱,蘇培陞,「提升SoC開發效益導入ESL設計刻不容緩」,[Online]. Available:http://www.mem.com.tw/article_content.asp?sn=0701020849 [10] Tim Kogel, Anssi Haverinen. "OCP TLM for Architectural Modelling," In Forum on specification and Design Languages, FDL 2005, Lausanne, Switzerland, Sept., 2005, pp. 225-244 [11] OSCI SystemC TLM-2.0 Standard, www.systemc.org/downloads/standards/TLM_2_0_LRM.pdf [12] L. Cai, D. Gajski, "Transaction Level Modeling: An Overview", in Proc. Int. Conf. Hardware/Software Codesign and Syst. Synthesis, Newport Beach, CA, Oct. 2003, pp. 19-24. [13] Open SystemC Initiative (2004). [Online]. Available: http://www.systemc.org [14] David C. Black, Jack Donovan, SystemC: From the Ground Up, Springer-Verlag New York, Inc., Secaucus, NJ, 2005 [15] E. Bernard, J.G. Krammer, M. Sauer, and R. Schweizer, “A pipeline architecture for modified higher radix FFT,” Int. Conf. Acoust. Speech Signal Process., Mar. 1992, pp.617-620 [16] L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “A new VLSI-oriented FFT algorithm and implementation,” ASIC Conf., Sep. 1998, pp.337-341. [17] G. Jo Byung and H. Sunwoo Myung, “New Continuous-Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy,” IEEE Trans. Circuits Syst. Regul. Pap.,vol. 52, no. 5, pp.911-919, May 2005. [18] Y.J. Moon and Y.I. Kim, “A mixed-radix 4-2 butterfly with simple bit reversing for ordering the output sequences,” Int. Conf. Adv. Commun. Technol., Feb. 2006, pp. 4-7. [19] C. T. Leondes and D. D. Rivers, “Frequency Domain Interpolation”, IEEE Trans. Aerospace and Electronic Systems, Vol. AES-13, no. 3, pp. 323-327, May 1977. (Frequency Interpolation) [20] H.M. Finn and R.S. Johnson, “Adaptive detection mode with threshold control as a function of spatially sampled clutter-level estimates,” RCA review, 29, pp. 414-464, Sep. 1968. [21] H. Rohling, “Radar CFAR Thresholding in Clutter and Multiple Target Situations,” IEEE Transactions on Aerospace and Electronic Systems, AES-19, pp. 608 – 621, July 1983. [22] R. Cumplido, C. Torres and S. Lopez, “On the implementation of an efficient FPGA-based CFAR processor for target detection”,1stInternational Conference on EEE, pp. 214-218, June 2004. [23] B. Magaz and M.L. Bencheikh, “An Efficient FPGA Implementation of The OS-CFAR Processor”, International Radar Symposium, pp. 1-4, May 2008. [24] XingLi, “Adaptive network fuzzy inference system used in interference cancellation of radar seeker,” IEEE Int’l Conf. on Intelligent Computing and Intelligent Systems, Oct. 2010.(clutter cancellation) [25] CHEN Da-li, XUE Ding-yu, GAO Dao-xiang, "New efficient fuzzy weighted filter approach for removal mixed noise," in Journal of System Smiulation, 2007,19(3), pp. 527-530. [26] ER M J, SIA A M, "Adaptive noise cancellation using dynamic fuzzy neural networks algorithm," in Proceedings 15th of IFAC World Congress, Barcelona, Spain 2002, pp. 352-357. [27] Greco M., Gini F, Farina A, “Radar Detection and Classification of Jamming Signals Belonging to a Cone Class”IEEE Trans. Signal Processing, Vol.56 Issue.5, pp. 1984 – 1993, May 2008 [28] T. Grotker, S. Liao, G. Martin, S. Swan, "System Design with SystemC," Kluwer Academic, Norwell, Mass, USA, 2002 [29] F. Ghenassia, "Transaction Level Modeling with SystemC," Springer, 2005 [30] Pasrieha S, "Transaction level modeling of SOC with SystemC 2.0," in Proceedings of Synopsys User Group Conference, San Jose, 2002, pp.236-240 [31] C.K. Chang, C.-P. Hung, and S.-G. Chen, "An Efficient Memory-based FFT Architecture," in Proc. of IEEE Int. Symp. on Circuits and Systems, 2003, pp. 129-132. [32] Y.N. Chang, K.K. Parhi, "An efficient pipelined FFT architecture,"IEEE Trans. Circuit Syst. II, Analog Digit. Signal Process. , vol. 50, no. 6, pp.322-325, Jun. 2003 [33] Cheng-Ru Hong , Yin-Tsung Hwang, and others, “Programmable AND-CFAR Signal Detector Design and Its FPGA Prototyping for FMCW Radar Systems,” in Proc. of 2011 VLSI-DAT, Hsinchu, 2011 [34] Zhiru Zhang, Deming Chen, "Challenges and opportunities of ESL design automation ," IEEE Conf. Solid-State and Integrate Circuits Technology(ICSICT), Oct. 2012, pp.1-4
摘要: 由於系統晶片的發展規模越趨龐大與複雜,大幅地增加了設計流程中系統的模擬與驗證困難度,同時也耗費了更多的時間與成本進行開發。為了解決此一問題,將晶片設計提升至更高的抽象層級成為唯一可行的解決方法,如此將有助於提供更完整以及快速的驗證方式。有鑑於此,本論文介紹了電子系統層級設計方法,並將其應用在調頻連續波(frequency-modulated continuous wave, FMCW)雷達系統設計上,開發一套配有多個功能模組的基頻處理器,以支援距離與速度量測所需要的各種DSP操作。在詳細設計之前,首先會分別針不同的系統架構進行評估,其中包含了直接連接(direct connect)與共享匯流排(share bus)兩種基頻系統架構,前者為所有功能模組透過專用的線路進行連接,後者則將所有功能模組掛載至一個數據匯流排上。本文利用統一建模語言SystemC於交易級(Transaction Level)中分別對於兩種架構進行建模與效能評估,將一些效能分析的選項添加至模型中,使得各項性能指標可在執行時進行收集。而分析的結果指明了直接連接系統架構所具有的優勢,而此雛型也會作為下層暫存器傳輸級(Register Transfer Level)編碼與細節設計時的依據。此外,管線化技術也被應用至其中以增加設計的吞吐率。所得到的基頻處理系統包含了一套傅立葉轉換處理器,一套頻率內插模組,一套AND-CFAR偵測模組以及一套距離運算模組。傅立葉轉換處理器所支援的點數大小為1024點,並使用Radix-2演算法與Memory-based架構進行設計,在操作頻率10MHz下用以計算出接收信號的頻譜;頻率內插模組可利用連續兩次快速傅立葉轉換的結果,針對偵測模組所偵測到帶有目標物拍頻訊息的頻帶執行頻率內插,以獲得更高解析度的頻譜,有利於更精確的速度以及距離量測;AND-CFAR偵測模組的目的則在於從計算出來的頻譜中檢測出目標物拍頻成分所在頻帶,偵測模組在固定虛警率為 的規範下試圖設計出最大的偵測機率,偵測機率 的設計規格為雷達操作在SNR值介於25dB到34dB的環境中能夠符合 。除了這些基本的模組之外,此系統還配有一操作在兩個階段的回波干擾消除模組,第一階段用於建構回波模型,並在第二階段中將所預估的回波由接收到的信號中移除,如此將有助於減少回波干擾以獲得更為清晰的訊號偵測,提高脈波鑑別的正確率。 經過RTL 編碼後,整個設計在Xilinx Virtex-IV XC4VLX60-10FF1148 FPGA實現。實現報告顯示,所需之硬體資源包括4796 logic slices,18個嵌入式乘法器模組以及7個18kb大小的BRAM記憶體模組。最大的工作頻率則可達到59.1 MHz,符合即時處理的速度要求。
As the development of a SoC growing more and more complicated, the complexity of system simulation and verification has increased dramatically. In the meantime, the development process is costly and time consuming. To mitigate the problem, raising the chip design to a higher abstraction level is the only viable solution. In view of this, this thesis introduces the methodology of Electronic System Level (ESL) Design and applies it to the baseband processor design for a frequency-modulation-continuous-waveform (FMCW) radar system. The base band processor is equipped with multiple functional modules to support various DSP operations needed in distance and velocity estimations. Prior to the detailed design, two system architecture alternatives are evaluated first. These include a “direct connect” architecture, where all functional modules are connected via dedicated links; and a “shared bus” architecture, where all function units are mounted to a data bus. The evaluation starts with the modeling of two architecture alternatives at the transaction level modeling using SystemC. Several profiling options are added to the modeling so that various performance indexes can be collected. The profiling result suggests the superiority of the direct-connect architecture. Lower level Register Transfer Level (RTL) coding then follows to model the design details. Extra pipelining techniques are also applied to enhance the throughput rate of the design. The resultant baseband processing system consists of a FFT processor, a frequency interpolation module, an AND-CFAR detection module, and a distance calculation module. The FFT processor is of size 1,024 and adopts a Radix-2 computing algorithm and a processor-memory architecture. It is meant for calculating the spectrum of the received signal under a 10MHz operation frequency. The frequency interpolation module is employed to enhance the spectral resolution. It uses the results of two consecutive FFTs to obtain a high resolution spectrum, which facilitates a more accurate distance and velocity measurement. The AND-CFAR detection module aims at identifying the beat frequency component of the target from the calculated spectrum. The detection is subject to a false alarm rate constraint of while trying to maximizing the detection rate. The design specs of the detection rate is when operating under an environment with SNR values ranging from 25dB to 34dB. Besides these basic modules, the system is further equipped with a clutter interference cancellation module operating in two phases. In phase one, the clutter model is first constructed. In phase, the estimated clutter is removed from the spectrum of the received signal. The cancellation measure helps reduce the interference for a cleaner signal detection. After RTL coding, the entire design is implemented in a Xilinx Virtex-IV FPGA. The implementation report shows the consumed hardware resources including 4796 logic slices, 18 embedded multipliers and seven 18kb BRAM modules. The maximum working frequency can reach 59 MHz, which meets the real time processing speed requirements.
URI: http://hdl.handle.net/11455/9067
其他識別: U0005-2708201316054300
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2708201316054300
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