Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/91096
標題: 應用於V頻段無線通訊系統之功率放大器設計
Design of Power Amplifiers for V-Band Wireless Communication System
作者: 張堂裕
Tong-Yu Chang
關鍵字: V-band
Power amplifier
TSMC CMOS 90nm process technology
Power-combining technique
Class AB power amplifier
Common-source stage
Microstrip line
Marchand balun
Cascode technology
Wilkinson divider/combiner
Transformer
V頻段
功率放大器
TSMC CMOS 90nm製程技術
功率組合技術
AB類功率放大器
共源級放大器
微帶線
Marchand平衡與不平衡轉換器
疊接級放大器
Wilkinson分配器以及組合器
變壓器
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摘要: This thesis presents the designs of power amplifier for V-band wireless communication system using TSMC CMOS 90-nm process technology. The power amplifiers that using power-combining technology are manufactured for V-band millimeter wave application. The content includes the circuit design, simulation analysis, chip measurement results, and a short discussion. This thesis consists of five main parts: In Chapter one, we will briefly introduce our research background and review some related studies before. In Chapter two, we will present the various types of power amplifiers, design issues, impedance matching methods, and also introduce the power-combining techniques. The first design of class AB power amplifier for V-band application is presented in Chapter three. It is consisted of three common-source stages and using Marchand balun for power-combining in the third stage. The design of microstrip line and Marchand balun is also presented in this chapter. The measured output power of 1-dB gain compression (OP_1dB) is 7.277 dBm, the saturated output power (P_sat) is 8.809 dBm, the maximum power-added efficiency (PAE_(_max)) is 1.809% , the maximum power gain (G_(P_max)) is 5.441 dB, the power consumption is 215 mW, and the chip size is 0.763 × 0.734 mm^2.   The second design of class AB power amplifier for V-band application is presented in Chapter four. It is also consisted of three stages. The first stage is adopts cascode configuration in which a short length of microstrip line is added at the gate of the common-gate stage to boost the gain. The second stage is splitted into two ways and adopts the common-source configuration. The third stage is four-way configuration and adopts the common-source configuration too. It uses Wilkinson divider/combiner and transformers for power-combining technique. The design of Wilkinson divider/combiner and transformers is also presented in this chapter. The output power at 1-dB gain compression (OP_1dB) is 7.285 dBm, the saturated output power (P_sat) is 10.649 dBm, the maximum power-added efficiency (PAE_(_max)) is 4.933% , the maximum power gain (G_(P_max)) is 17.159 dB, the power consumption is 234 mW, and the chip size is 1.098 × 0.633 mm^2. In Chapter five, we make a simple conclusion and shortly discuss the possible study for the future work.
本論文探討應用於V頻段無線通訊系統之功率放大器設計,利用國家晶片中心所提供的TSMC CMOS 90nm製程技術,在V頻段以功率組合技術設計功率放大器,內容包含電路及元件設計、模擬分析、晶片量測、結果討論。論文整體主軸可分為五大部分: 第一章簡述研究背景,並對過去的相關研究做一個簡單的介紹。 第二章對功率放大器的分類及設計考量作介紹,同時簡述阻抗匹配以及功率組合技術。 第三章設計了一個應用在V頻段的AB類功率放大器,採用三級的共源級架構實現,並於第三級加入Marchand平衡與不平衡轉換器實現功率組合技術,當中簡述微帶線以及Marchand平衡與不平衡轉換器的設計。其輸出1dB增益壓縮點OP_1dB為7.277dBm、飽和輸出功率P_sat為8.809dBm、功率附加效率極值PAE_(_max)為1.809%、功率增益極值G_(P_max)則為5.441dB、功耗為215mW、晶片面積則為0.763×0.734mm^2。 第四章設計了第二個應用在V頻段的AB類功率放大器,增益級為疊接組態,並在上方共閘級的閘端加入一小段長度的微帶線以提升增益,驅動級為兩路的共源級組態,功率級則為四路的共源級組態,利用Wilkinson分配器以及組合器、變壓器實現功率組合技術,當中簡述Wilkinson分配器以及組合器、變壓器的設計。其輸出1dB增益壓縮點OP_1dB為7.285dBm、飽和輸出功率P_sat為10.649dBm、功率附加效率極值PAE_(_max)為4.933%、功率增益極值G_(P_max)則為17.159dB、功耗為234mW、晶片面積則為1.098×0.633mm^2。 第五章總結各章的研究成果並探討未來的研究與改進方向。
URI: http://hdl.handle.net/11455/91096
其他識別: U0005-2501201512543200
文章公開時間: 2018-01-28
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