Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/91193
標題: 低功耗十一位元單端輸入具反向器架構之連續逼近式類比數位轉換器及靜電防護設計
An 11-bit single-ended inverter-based successive approximation analog to digital converter for low power and ESD design
作者: 鄭冠偉
Guan-Wei Jeng
關鍵字: SAR ADC
inverter-based
low power
ESD design
連續逼近式類比數位轉換器
反向器架構
低功耗
靜電防護設計
引用: [1] W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens,'A 3b 40 GS/s ADC-DAC in 0.12 μm SiGe,' in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 262–263. [2] S. Shahramian, S. Voinigescu, and A. Carusone, 'A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees, ' IEEE journal of solid-state circuits, vol. 44, p. 1709, 2009. [3] S.-C. Lee, Y.-D. Jeon, J.-K. Kwon, and J. Kim, 'A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications, ' IEEE Journal of Solid-State Circuits, vol. 42, pp. 2688-2695, 2007. [4] K. Chandrashekar, M. Corsi, J. Fattaruso, and B. Bakkaloglu, 'A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling, ' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, pp. 602-606, 2010. [5] H. C. Hong and G. M. Lee. 'A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC'. IEEE J. Solid-State Circuits, vol. 42, pp. 2161-2167, Oct. 2007. [6] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, 'A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,' IEEE J.Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010. [7] Gil-Cho Ahn et. al., 'A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators,' IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005. [8] K. Doris, E. Janssen et al, 'A 480mw 2.6GS/s 10b 65nm CMOS Time- Interleaved ADC with 48.5dB SNDR up to Nyquist,' ISSCC Dig. Tech. Papers, pp. 180-181, 2011. [9] A. M. A b and P. R. Gray, 'A 1.5 V, 10 bits, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE J. Solid-state Circuits, vol. 34, pp. 599-604, May 1999. [10] Rajshekhar G and M S Bhatt (2008),'Design of resolution adaptive TIQ Flash ADC using AMS 0.35μm technology' 2008 international conference on electronic design, December 1-3 Penang, Malaysia.pp 1-6. [11] Baljit Singh and Praveen Kumar (2009), 'Characterization analysis of a High speed,Low Resolution ADC based on simulation results for different resolutions',International conference on information and multimedia technology, pp533 – 537. [12] Ivan Piatak, Dmitry Morozov,Johann Hauer, 'An inverter-based 6-bit Pipelined ADC with low power consumption,' EUROCON, 2013 IEEE, pp. 1951–1954, 2013 [13] Ivanildo Jose Pereira Gomes,'Low Power Analog-to-Digital Converter for Visual Prosthesis,' MS. dissertation, University tecnica de Lisba, Oct 2009. [14] M. V. Elzakker, et al., 'A 1.9W 4.4fJ-Conversion-step 10b 1MS/s Charge-Redistribution ADC, ' ISSCC Dig. Tech. Papers,pp. 244-245, Feb. 2008. [15] Xingyuan Tong, Zhangming Zhu, and Yintang Yang, 'Low Power Capacitor Arrays for Charge Redistribution SAR A/D Converter in 65nm CMOS,' PACCS 2009, in press. [16] B. P. Ginsburg, et al., '500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,' in IEEE J. Solid-State Circuits, vol.42, no. 4, pp. 739-747, Apr. 2007. [17] Y.-K. Chang et al., 'A 8-bit 500kS/s low power SAR ADC for biomedical application,' in Procs. IEEE ASSCC, Nov. 2008, pp. 228–231. [18] Ginsburg and Chandrakasan. 'An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC' Circuit and System, 2005. ISCAS 2005. IEEE International Symposium on (2005) pp. 184 – 187 vol. 1. [19] X. Zou, X. Xu, L. Yao, and Y. Lian, 'A 1-V 450-nW fully integrated programmable biomedical sensor interface chip,' IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1067–1077, Apr. 2009. [20] ESD Protection in CMOS ICs (Prof. M-D Ker): http://www.ics.ee.nctu.edu.tw/~mdker/ESD/. [21] A. Boni, A. Pierazzi, and D. Vecci, 'LVDS I/O interface for Gb/sper- pin operation in 0.35μm-CMOS,' IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706–711, Apr. 2001. [22] 陳世宏、柯明道、莊哲豪、陳子平, '0.18 微米互補式金氧半類比輸出/輸入電路之靜電放電故障分析', 工業技術研究院/系統晶片技術發展中心 [23]'STC Pure 1.8V Linear I/O Library in 0.18-μm CMOS Process', 工業技術研究院/系統晶片技術發展中心
摘要: By the progression of technology, the size of CMOS devices have been reduced constantly, which effectively shrinks the area of chip and let the standard of Analog to Digital Converters have completely new development, a low speed ADC can be widely used in Biomedical Systems and portable electronics products, the appearance of many electronic products have became light, thin, short and small so that we find the quantity of electric charge is limited, and that's why we have to design a low power consumption circuit to improve this problem. In addition, our laboratory had used the process by 90nm to carry out high-speed analog to digital converters in last two years, the device size in advancing process is smaller than others, and gate oxide layer tends to suffer from external Electrostatic damage such as HBM and MM, as a result, we start to construct ESD protection circuit in order to protecting Internal circuit from Electrostatic damage. This essay realizes a Analog to Digital Converters, the process used TSMC 0.35μm CMOS Technology, the resolution of 11 bits, the framework for the successive approximation analog to digital converter, the goal of this designation is to reduce the power consumption, which mainly improve comparator and capacitor array's switch consumption, comparator used inverter-based, Taking capacitor array and switch apart A-side and B-side, we can carry out the first comparison without switching any after sampling phase, In addition let sample and hold circuit used Bootstrapped switch can improve the decrease SNDR range when Input frequency closes Nyquist Rate. In Supply voltage is 1.2V、Input Frequency is 1.64kHz、VPP is 3V、Sampling frequency is 25kS/s;the result of the survey is that DNL is 0.88/-0.90 LSB、INL is 0.72/-1.14 LSB、SNDR is 63.76 dB、SFDR is 73.99dB、ENOB is 10.28bit、power consumption is 3.37μW、FOM is 181 fJ/Conv.-setp、chip area is 1.41mm2(exclusive of PAD).In ESD protection circuit, the process is TSMC 0.18μm CMOS Technology, and in the mode of HBM, the endurance capacity of input pin is about ±150V, and the endurance capacity of output pin is about ±450V.
隨著科技的進步,CMOS元件尺寸不斷微小化,有效縮小晶片面積,也使類比數位轉換器規格有全新的發展,一個低取樣速度的類比數位轉換器可以廣泛的運用在生醫系統及攜帶式電子產品,許多電子產品外觀演變成輕、薄、短、小,這個演變也須關注到電池電量受限,因此必須設計出低消耗功率的電路以改善此問題。此外,本實驗室近兩年內使用90奈米的製程實現高速的類比數位轉換器,在先進的製程內元件尺寸較小,閘極氧化層易受外在靜電打穿,如人體放電模式及機械放電模式,因此開始建立靜電防護電路,以保護內部電路不受外界靜電破壞。 本篇論文實現一個類比數位轉換器,製程使用TSMC 0.35μm CMOS技術,解析度為11位元,架構為連續逼近式類比數位轉換器,以低功耗為設計目標,主要改善比較器及電容陣列的開關功耗,比較器使用具反向器的架構,電容陣列分解成A-side及B-side,在取樣後不需要切換任何開關可執行第一次的比較,另外取樣保持電路使用Bootstrapped switch,可改善輸入頻率接近Nyquist Rate時訊號對雜訊與諧波失真比下降的幅度,在電壓1.2V、輸入頻率1.64kHz、VPP為3V、取樣頻率25kS/s;經量測後,微分非線性誤差為0.88/-0.90 LSB、積分非線性誤差為0.72/-1.14 LSB、訊號對雜訊與諧波失真比為63.76 dB、無雜散動態範圍(SFDR)為73.99dB、有效位元數為10.28bit、消耗功率為3.37μW、轉換效率為181fJ/Conv.-setp、晶片佈局面積為1.41mm2(不含PAD)。靜電防護電路方面,製程使用TSMC 0.18μm CMOS技術,在人體放電模式下,輸入腳位的靜電承受能力約為±150V,輸出腳位的靜電承受能力約為±450V。
URI: http://hdl.handle.net/11455/91193
其他識別: U0005-3103201408401800
文章公開時間: 2017-03-31
Appears in Collections:電機工程學系所

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