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標題: 低功耗逐步近似暫存式類比數位轉換器設計
Low Power Successive Approximation Register Analog to Digital Converter Design
作者: 葉昆明
Kun-Ming Yeh
關鍵字: ADC
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摘要: This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch are used.   The SAR ADC is designed and simulated by HSPICE with TSMC 0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS technology. The supply voltage of the 8-bit SAR ADC is 1.8V and the sampling rate is 5KHz. Its power consumption is 1100μW.
本論文之內容為設計一類比數位轉換器,使其具備低功率。適用於可攜式電子產品,例如:手機、數位相機、PDA……等等。為了降低轉換時的功率消耗,採用逐步近似暫存器式類比數位轉換器,八位元逐步近似暫存器式類比數位轉換器採用二進制搜尋的電荷分配數位類比轉換器來增加其電路線性度與精度,為了兼顧速度與功率消耗採用僅鎖存比較器與拔靴帶式開關的組合實現;電路模擬方面,是利用HSPICE進行模擬。   此類比數位轉換器是使用台灣積體電路製造股份有限公司所提供的0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS製程技術來設計與製造,並利用Hspice進行電路模擬。在供應電壓1.8V下,此八位元類比數位轉換器的取樣頻率為5KHz,功率消耗為1100μW。
其他識別: U0005-2310201315135900
文章公開時間: 2016-12-30
Appears in Collections:電機工程學系所



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