Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/91213
標題: 八位元每秒二十六億次時序交錯連續逼近暫存式類比數位轉換器之校正
Calibration of a 2.6GS/s 8 bits Time-interleaved SAR ADC
作者: 蔡秉均
Bing-Jun Tsai
關鍵字: SAR ADC
time-interleaved
timing skew calibration
連續逼近暫存式類比數位轉換器
時序交錯式
時脈偏移校正
引用: [1] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, CMOS data converters for communications, Kluwer Academic Publishers,Boston, 2000. [2] Naoki KUROSAWA, Kaoru MARUYAMA,Haruo KOBAYASHI, Hidetake SUGAWARA and Kensuke KOBAYASHI, 'Explicit Formula for Channel Mismatch Effects in Time-Interleaved ADC Systems,'IEEE 2000. [3] Yih-ChyunJenq, 'Digital Spectra of Nonuniformly Sampled Signals: A Robust Sampling Time Offset Estimation Algorithm for Ultra High-speed Waveform Interleaving,' IEEE Transactions on Instrumentation and Measurement, VOL. 39. NO. 1, Feb 1990. [4] DušanStepanović and BorivojeNikolić, 'A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,' IEEE JSSC, Vol. 48, No. 4, April 2013. [5] Erwin Janssen, Kostas Doris, Athon Zanikopoulos, Alessandro Murroni, Gerard van der Weide, Yu Lin, Ludo Alvado, Frederic Darthenay, YannickFregeais, 'An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS,' IEEE ISSCC, February 2013. [6] SandipanKundu, Julia H. Lu, ErkanAlpman, HasnainLakdawala, JeyanandhParamesh, Byunghoo Jung, SaritZur, Eshel Gordon, 'A 1.2 V 2.64 GS/s 8bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN,' IEEE CICC, 2014. [7] Hao Huang, Markus Grözing, Johannes Digel, DamirFerenci, Felix Lang, Manfred Berroth, 'A 6-GS/s 6-bit Time Interleaved SAR-ADC,' proc. in the 8th European Microwave Integrated Circuits Conference, Oct 2013. [8] 張峻豪,'高輸入頻寬之高速非同步連續逼近式類比數位轉換器',國立中興大學碩士論文,中華民國一百零四年一月。 [9] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure', IEEE J. Solid-State Circuits, Vol. 45, NO. 4, April 2010. [10] Hari Shanker Gupta, RM Parmar and RK Dave, 'High Speed LVDS Driver for SERDES,' ELECTRO, Varanasi, pp. 92-95, 22-24 Dec. 2009. [11] Yih-ChyunJenq,'Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High-speed Waveform Digitizers,'lEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 37, NO. 2. JUNE 1988 [12] Chun-Chend Huang, Chung-Yi Wang, and Jieh-Tsorng Wu, 'A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques,' IEEE Journal of Solid-State Circuits, vol. 46, No. 4, April 2011. [13] M. El-Charnmas and B. Murmann, 'A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,' IEEE J. Solid-State Circuits, vol. 46, pp. 838-847, April 2011. [14] Behzad Razavi, 'Problem of Timing Mismatch in Interleaved ADCs,' Electrical Engineering Department University of California, Los Angeles, 2012. [15] M. El-Charnmas and B. Murmann, 'General analysis on the impact of phase-skew in time-interleaved ADCs,' IEEE Tran. Circuits Syst. I, vol. 56, pp. 902-910, May 2009. [16] Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, and Gerard van der Weide, ?A 480mW 2.6GS/s 10b Time-Interleaved ADC With 48.5dB SNDR up to Nyquist in 65nm CMOS,? IEEE Journal of Solid-State Circuits, vol. 46, NO. 12, December 2011. [17] Pieter J. A. Harpe, Ben Büsze, Kathleen Philips, and Harmke de Groot, 'A 0.47-1.6mW 5-bit 0.5-1GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios,' IEEE Journal of Solid-State Circuits, vol. 47, NO. 7, JULY 2012. [18] Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, and Bram Nauta, 'A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS,' IEEE Journal of Solid-State Circuits, vol. 43, NO. 4, April 2008. [19] K. Poulton et al., 'A 20-Gsample/s 8 b ADC with 1-MByte memory in 0.18- CMOS,' IEEE ISSCC Dig. Tech. Papers, pp. 318–319, Feb. 2003. [20] D. Greshishchev et al., 'A 40 GS/s 6 b ADC in 90 nm CMOS,' IEEE ISSCC Dig. Tech. Papers, pp. 390–391, Feb. 2010.
摘要: This thesis presents a Time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) with timing skew calibration. For upgrading the sampling rate of ADC, we choose the architecture of time-interleaved, but the architecture of time-interleaved also brings on three mismatch : timing skew, gain error, and offset error. So we use timing skew calibration circuits to cancel the bad effect of time-interleaved. This Time-interleaved SAR ADC chip was fabricated under TSMC 90nm GUTM. Before calibrations, it was measured 4.7bits at low input frequency and 2.69bits at high input frequency, after offset & timing skew calibration, it was became 5.0 bits at low input frequency and 4.38 bits at high input frequency. The measured power consumption is 158mW, and the FOM is 3404 fJ/conversion-step.
本論文呈現一時序交錯連續逼近式類比數位轉換器並加入時脈偏移校正,採用時序交錯的架構,目的是為了提升取樣頻率,但因著時序交錯式的架構會帶來三種典型的mismatch:時脈偏移(Timing skew),增益誤差(Gain error)和偏移誤差(Offset error)。所以我們加入時脈偏移校正電路,以挽救時序交錯式架構所帶來不好的影響。 在TSMC 90nm GUTM製程下,Time-interleaved SAR ADC未校正前,量測低頻4.7bits,高頻2.69bits,經過Offset&Timing skew的校正後,量測低頻5.01bits,高頻4.38bits。功耗為158mW,FOM為3404fJ/conversion-step。
URI: http://hdl.handle.net/11455/91213
其他識別: U0005-2508201511534900
文章公開時間: 2018-08-27
Appears in Collections:電機工程學系所

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