Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/91524
標題: 以石墨烯當導電層與阻障層用於矽通孔之電鍍填充
Using Graphene as Conducting Layer and Barrier Layer for Through Silicon Via Filling by Electroplating
作者: Shih-Cheng Chang
張世誠
關鍵字: Graphene
Through silicon via
Nickel-Tungsten Alloy
Barrier Layer
Electroplating
石墨烯
矽通孔
鎳鎢合金
阻障層
電鍍
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摘要: 微電子技術、微機電系統及微光機電系統近年主要的研究焦點皆放在三維晶片堆疊,其中矽通孔在連結三維積體電路晶片的堆疊扮演關鍵性的角色。矽通孔最主要的功能是減少晶片與晶片之間的垂直距離,此舉可以減少晶片的體積更能訊號延遲的疑慮。矽通孔的發展中電化學沉積技術扮演決定性的角色,尤其是金屬銅的電化學沉積,在三維晶片封裝中是關鍵性且廣受使用的技術。 石墨烯材料由於它優異的導電性與導熱性近幾年被廣受注目。製備石墨烯的方式有很多,其中成本較低且有可能商品化的是化學氧化還原石墨烯法,該製備方式的應用面很廣,因為氧化的石墨烯具備許多的含氧官能基,這些親水性的官能基能讓氧化石墨烯穩定分散在水及其他溶劑中,所以非常適合用於基材表面濕製程化學接枝石墨烯的應用。 矽通孔銅製程技術目前遇到的問題是熱機械應力,由於銅與矽的熱膨脹係數差異很大,在熱信賴度的測試會面臨孔裡因銅膨脹而破裂或擠壓。解決的辦法是沉積熱膨脹係數與矽最接近的導電金屬鎢,但是鎢不能使用濕式電鍍沉積只能用化學氣相沉積或物理氣相沉積,但鎢可以與磁性材料鎳一族共同沉積,故濕式電鍍沉積鎳鎢合金將會是解決選項之一。此外,有鑑於石墨烯之優良的導電性及熱膨脹係數與矽十分接近的特點,因此本論文選用石墨烯當作矽通孔晶種層。 本研究致力於使用新穎的石墨烯材料當作雙功能的晶種層與阻障層,且利用濕式電鍍鎳鎢合金解決熱膨脹問題,開創全濕製程、無熱膨脹問題之無銅矽通孔填孔電鍍製程。
Three-dimensional (3D) chip stacking is a major focus in recent research and development of microelectronics, MEMS, and MOEMS technology. Through silicon vias (TSV) play a key role in the 3D IC chip stacking connections. A main advantage of TSV is to make the shortest chip-to-chip vertical interconnection, which allows for size reduction of the chip and reducing signal transmission delay. Electrodeposition plays an important role in TSV development, especially copper electrodeposition, which is a critical technology and generally used in the 3D chip packaging. Graphene materials, including single layer and multi layer graphene platelet, have recently drawn extensive attention due to their outstanding electrical and thermal properties. Reduction of graphene oxide (GO) is a method for preparaing the graphene film. Since GO has a large amount of oxide functional groups, it can be well dispersed in several solvents and enable it to be coated on a substrate by a chemaical grafting method using a wet process. In TSV technology, the thermo-mechanical fatigue may lead to failure in the TSV interconnects, because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The package materials with different CTEs will induce large stresses at interfaces. To overcome this problem, we should choose tungsten to substitute copper. However, tungsten cannot be directly plated from an aqueous electrolytes but can be deposited by chemical vapor deposition or physical vapor deposition. Fortunately, tungsten it can be co-deposited with iron group metals. Alternatively, since the CTE of graphene is closer to silicon than copper, we choose graphene sheets to substitute copper seed layer. In our research, we reduce the procedure of TSV fabrication using a wet process to substitute barrier and seed layer with graphene, and electrodeposition with Ni-W alloy to make a copper-free process.
URI: http://hdl.handle.net/11455/91524
其他識別: U0005-1107201413080000
文章公開時間: 10000-01-01
Appears in Collections:化學工程學系所

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