Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9178
標題: 利用CMOS技術設計與分析RF接收器
Design and Analysis on RF Receiver in CMOS Technology
作者: 周以德
Chou, Yi-Te
關鍵字: W-band低雜訊放大器
W-band low noise amplifier
24GHz的接收器
802.11a頻段接收器
24GHz超外差系統的前端電路
24GHz direct-conversion receiver
802.11a receiver
24GHz super-heterodyne receiver frontend
出版社: 電機工程學系所
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摘要: 本論文主要分為四個主題,第一個主題為利用TSMC 90nm CMOS的製程,設計應用於汽車防撞雷達W-band的低雜訊放大器(LNA),使用共平面波導的傳輸線設計輸入與輸出阻抗匹配與佈局的走線,而此傳輸線使用ground shielding的技巧來提高Q值以減少訊號傳輸時對於基底的損耗。本章節有探討如何選擇電晶體的尺寸以及偏壓點,利用noise模型推導出較低雜訊指數的電晶體尺寸與被動元件。而實際量測後,操作頻率78GHz的輸入與輸出阻抗匹配皆有在-10dB以下,增益為12.57dB,3dB頻寬為74GHz-90GHz,IIPᴣ為-8.1dBm,雜訊指數為6.07dB,與相同頻帶的先前文獻比較,本篇論文的雜訊指數算是較低的,而量測之功率消耗為28.56mW。 第二個主題是利用TSMC 0.18µm CMOS的製程,設計應用於24GHz的接收器,利用三級的疊接架構LNA提高增益,並利用主動Balun將訊號單轉雙,混頻器使用雙端平衡式混頻器,使用主動負載降低功率,並在轉導級電晶體汲級加上電感消除寄生電容。而實際量測後,操作頻率的輸入與輸出阻抗匹配皆有在-10dB以下,轉換增益為18.7dB,IIPᴣ為-22dBm,雜訊指數為8.63dB,而量測之功率消耗為62.3mW。 第三個主題是利用TSMC 0.18µm CMOS的製程,設計應用於802.11a頻段的接收器,採用的LNA為電流再利用的架構,而混頻器的切換級採用PMOS來降低操作電壓。模擬結果輸入與輸出阻抗皆為-10dB以下,轉換增益為31.56dB,雜訊指數為9.22dB,IIPᴣ為-32dBm, P1ɗB為-41dBm,而消耗功率為41mW。 第四個主題為利用TSMC 0.18µm CMOS的製程設計24GHz超外差系統的前端電路,利用三級疊接組態的LNA串接單端平衡混頻器來完成,使用單端平衡式混頻器可減少訊號單轉雙的困難。量測結果轉換增益為20.4dB,線性度IIPᴣ為-22dBm,P1ɗB為-12dBm,雜訊指數為8.37dB,而整體的功率消耗為64.8mW,其中核心電路只有54mW。
The thesis includes four topics. The first design topic a low noise amplifier(LNA)in W-band that used in automotive collision avoidance radar and was fabricated in TSMC 90nm CMOS process. We used coplanar waveguide transmission line for input and output matching in layout, this kind of transmission line adopted ground shielding technique to enhance Q value and decrease signal loss from substrate. This chapter will discuss about how to design the dimension of transistor and proper bias, and also to derive a lower noise figure of the transistor size and passive components from noise model. The measurement shows input and output matching are under -10dB in the operation frequency 78GHz, gain is 12.57dB, 3-dB bandwidth is 74GHz-90GHz, IIPᴣ is -8.1dBm, and noise figure is 6.07dB. Compared with previous references in the same operation frequency, our design had better noise figure. Power consumption in measurement was 28.56mW. The second topic describes a 24GHz direct-conversion receiver which is fabricated in TSMC 0.18µm CMOS. This LNA uses three stages cascode topology to enhance gain, and employs an active balun to transfer single signal to differential. This mixer is double balanced type, and designs active loads to decrease power dissipation, it also parallels an inductor to eliminate parasitic capacitances between the drain of transistor on the transconductance stage. The measured input and output matching are under -10dB in the operation frequency, conversion gain is 18.7dB, IIPᴣ is -22dBm, and noise figure is 8.63dB. The measurement shows power consumption is 62.3mW. The third topic implement a direct-conversion receiver applied to 802.11a fabricated in TSMC 0.18µm CMOS. LNA is current reused topology, and mixer adopts PMOS transistor at switch stage to reduce headroom. The simulation results are input and output matching are under -10dB, conversion gain is 31.56dB, IIPᴣ is -32dBm, P1ɗB is -41dBm and noise figure is 9.22dB. Power consumption is 41mW. The forth topic introduces a 24GHz super-heterodyne receiver frontend uses in TSMC 0.18µm CMOS technology. This design uses three stages cascode topology LNA connects single balanced mixer, that can neglect the problem to transfer single signal to differential. After measurement, conversion gain is 20.4dB, IIPᴣ is -22dBm, P1ɗB is -12dBm and noise is 8.37dB. Power consumption ias 64.8mW, and core area is 54mW.
URI: http://hdl.handle.net/11455/9178
其他識別: U0005-0111201217050800
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0111201217050800
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