Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9276
標題: 應用於VP8以及H.264/AVC視訊標準區塊消除濾波器之硬體共享架構設計與實現
A Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Coding
作者: 周育霖
Chou, Yu-Lin
關鍵字: 區塊消除濾波器
H.264/AVC
硬體共享架構
VP8
Deblocking Filter
Hardware Sharing Architecture
出版社: 電機工程學系所
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Information technology advanced coding of audio and video Part 2: Video[S]. 2006. [8] V. Lappalainen, A. Hallapuro, T. Hamalainen, “Complexity of optimized H.26L video decoder implementation,” IEEE Trans. Circuits Syst. Video Technol., vol.13, no.7, pp. 717- 725, July 2003. [9] I. E. G. Richardson, “H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia,” John Wiley & Sons, 2003. [10] P. List, A. Joch, J. Lainema, G. Bjontegaard, and M. Karczewicz, “Adaptive deblocking filter,” IEEE Trans. Circuits Syst. Video Technol., vol.13, no.7, pp.614-619, July 2003. [11] M. Parlak, and I. Hamzaoglu, “Low power H.264 deblocking filter hardware implementations,” IEEE Trans. Consum. Electron., vol.54, no.2, pp.808-816, May 2008. [12] K. Xu, and C. S. Choy, “A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC,” IEEE Trans. Circuits Syst. Video Technol., vol.18, no.3, pp.363-374, March 2008. [13] H. C. Chung, Z. Y. Chen, and P. C. Chang, “Low power architecture design and hardware implementations of deblocking filter in H.264/AVC,” IEEE Trans. Consum. Electron., vol.57, no.2, pp.713-719, May 2011. [14] B. Sheng, W. Gao, and D. Wu, “An implemented architecture of deblocking filter for H.264/AVC,” in Proc. Int. Conf. Image Processing (ICIP), Oct. 2004, vol. 1, pp. 665- 668. [15] K. Y. Min, and J. W. Chong, “A memory efficient architecture of deblocking filter in H.264/AVC using hybrid processing order,” in Proc Int. SoC Design Conf. (ISOCC), Nov. 2009, pp.67-70. [16] G. Khurana, A. A. Kassim, T. P. Chua, and M. B. Mi, “A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC,” IEEE Trans. Consum. Electron., vol.52, no.2, pp. 536- 540, May 2006. [17] T. M. Liu, W. P. Lee, T. A. Lin, and C. Y. Lee, “A memory-efficient deblocking filter for H.264/AVC video coding,” in Proc. IEEE Int. Symp. Circuits Syst., May 2005, vol. 3, pp. 2140- 2143. [18] C. M. Chen, and C. H. Chen, “A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order,” in Proc. Int. Intelligent Sensors, Sensor Networks and Information Processing Conf., Dec. 2005, pp. 361- 366. [19] X. Chen, W. Xia, and X. Lu, “A high-throughput low-power hardware architecture for H.264 deblocking filter,” in Proc. Int. Conf. Computer Engineering and Technology (ICCET), Apr. 2010, vol.2, pp.V2-561-V2-565. [20] T. H. Tsai, and Y. N. Pan, "High efficient H.264/AVC deblocking filter architecture for real-time QFHD,” IEEE Trans. Consum. Electron. , vol.55, no.4, pp.2248-2256, Nov. 2009. [21] K. H. Chen, and H. P. Chen, “Quadruple filtering schedule for H.264/AVC deblocking filter,” in Proc. Int. Symp. VLSI Design, Autom. Test, Apr. 2010, pp.343-346. [22] J. Kim, and J. Jeong, “Adaptive Deblocking Technique for Mobile Video,” IEEE Trans. Consum. Electron. , vol. 53, no. 4, pp. 1694-1702, Nov. 2007. [23] S. C. Tai, Y. R. Chen, C. Y. Chen, and Y. H. Chen, “Low complexity deblocking method for DCT coded video signals,” IEE Proceedings Vision, Image and Signal Processing, vol. 153, no. 1, pp. 46- 56, Feb. 2006. [24] J. Kim, M. Choi, and J. Jeong, “Reduction of Blocking Artifacts for HDTV using Offset-and-Shift Technique,” IEEE Trans. Consum. Electron., vol. 53, no. 4, pp. 1736-1743, Nov. 2007. [25] S. Xu, L. Yu, and G. Zhu, “An Adaptive De-blocking Method based on Measuring Flatness of Macroblock,” in Proc. Int. Symp. Intelligent Signal Processing Communications (ISPACS), Dec. 2006, pp. 1-4. [26] C. A. Chien, H. C. Chang, and J. I. Guo, “A high throughput deblocking filter design supporting multiple video coding standards,” in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp.2377-2380. [27] T. M. Liu, W. P. Lee, and C. Y. Lee, “An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 7, pp. 937-943, July 2007. [28] S. C. Chang, W. H. Peng, S. H. Wang, and T. Chiang, “A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC,” IEEE Trans. Consum. Electron. , vol. 51, no. 1, pp. 249- 255, Feb. 2005. [29] J. Y. Lee, J. J. Lee, and S. M. Park, “Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism,” Circuits, Devices & Systems, IET , vol.4, no.2, pp.147-158, Mar. 2010. [30] Y. Li, Y. Qu, and Y. He, “Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder,” in Proc. IEEE Int. Symp. Circuits Syst., May 2007. pp. 2906-2909.
摘要: 本論文提出一個適用於VP8以及H.264/AVC多重視訊標準之硬體共享區塊消除濾波器設計。首先,我們重新整理原始視訊標準中區塊消除濾波器之相同點並提出一套適用於VP8以及H.264/AVC之硬體架構以達到硬體共享進而減少硬體面積。為了更進一步降低運算複雜度,我們,犧牲少許影像畫質,另外提出了一高度硬體共享之架構設計以獲得最大硬體共享。另一方面,為了節省區塊效應消除濾波器運算中所使用的記憶體空間,我們提出與移動補償電路之記憶體共享架構,利用重新安排區塊邊界的濾波器運算順序,進而有效配置記憶體存取並有效達記憶體共享。 實驗結果顯示,我們提出的高度硬體共享之架構設計比個別實現兩組視訊標準節省了63.3%之位移器,77.4%之加法器,以及100%之乘法器。整體而言,於VP8解碼器中,PSNR平均降低不到1%。最後,我們採用TSMC 0.18 μm cell library的製程進行電路實作,結果顯示本架構操作在130 MHz 的頻率下可完成Full HD 1080P@30fps的區塊消除濾波器的運算而Gate Count為43.2K。由結果顯示,本電路,可適用於VP8以及H.264/AVC視訊標準之編碼器與解碼器。
In this thesis, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture which is suitable for H.264/AVC and VP8. The proposed design is then reused for the whole filtering. To further reduce the computational complexity, highly sharing architecture is also presented. In order to save the size of the on-chip memory, a memory sharing architecture of the deblocking filter and motion compensation is introduced. We also reorganize the processing order of filtering to reduce the total on-chip memory size. According to the experimental results, the adopted hardware sharing architecture saves 63.3% of shifters, 77.4% of adders and 100% of multipliers totally. The overall PSNR drops less than 1% on the VP8 decoder for low complexity applications. Finally, a hardware implementation using TSMC 0.18 μm cell library is performed. The clock frequency of the proposed hardware is working at 130 MHz to perform deblocking filter for supporting Full HD 1080P@30fps. The implementation results show that the gate count of this architecture adopted on VP8 and H.264/AVC video codec system is 43.2K.
URI: http://hdl.handle.net/11455/9276
其他識別: U0005-2307201216330500
文章連結: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2307201216330500
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