Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/96999
標題: 物件偵測雷達系統子電路之研發
Subcircuits Study of a Radar System for Object Detection
作者: 陳慶豐
Ching-Fong Chen
關鍵字: CMOS90奈米製程
相移器
向量組合
低雜訊放大器
混頻器
電流注入技巧
接收端
威爾京生功率分波器
V頻段
W頻段
CMOS90nm process technology
phase shifter
vector combination
low noise amplifier
mixer
current bleeding
receiver
Wilkinson power divider
V-band
W-band
引用: [1] Vilhelm Gregers-Hansen, Radio Propagation at 90GHz Slides, Radar Division, Naval Research Laboratory, Presented at FCC Forum: “New Horizons: 90 GHz Technologies,” July 14, 2000 [2] D. K. Sheffer and T. H. Lee, “A 1.5 V, 1.5 GHz CMOS low-noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 745 - 759, May 1997. [3] D. K. Sheffer and T. H. Lee, “Corrections to “A 1.5 V, 1.5 GHz CMOS low-noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1397 - 1398, Jun. 2005. [4] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. P. de Gyvez, D. J. Allstot, and E. Sanchez-Sinencio, “A capacitor cross-couple common-gate low- noise amplifier,” IEEE Transactions on Circuits and Systems II, vol. 52, no. 12, pp. 875 - 879, Dec. 2005 [5] X. Fan, H. Zhang, and E. S. Sinencio, “A noise reduction and linearity improvement technique for a differential cascode LNA,” IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 588 - 599, March 2008. [6] B. Razavi, RF Microelectronics, Prentice Hall, 1998. [7] B. Razavi, RF Microelectronics, 2nd ed. Prentice Hall, 2011. [8] 吳明蔚, ‘‘應用於無線區域網路802.11a與60GHz之毫米波之功率放大器設計”,國立中興大學電機工程學系碩士學位論文, 2011年七月 [9] Yaoming Sun and Christoph J. Scheytt ,“A 360 degree phase shifter for 60 GHz application in SiGe BiCMOS technology,” Antennas and Electronics Systems, 2009 [10] 呂鎮安,‘‘應用於數位電視頻帶之平衡不平衡轉換器設計”,國立中央大學電機工程研究所碩士論文,六月,2007年。 [11] 陳思源,‘‘CMOS高耦合分波器之設計”,國立中興大學電機工程研究所碩士論文,七月,2009年。 [12] 賴思涵,‘‘CMOS微型化Balun之設計”,國立中興大學電機工程研究所碩士論文,七月,2008年。 [13] N. Marchand, “Transmission-line conversion transformers,” Electronics, vol. 17, no. 12, pp. 142-145, 1994. [14] Yikun Yu, et al., “A 60GHz digitally controlled phase shifter in CMOS,” European Solid State Circuits Conference (ESSCIRC), 2008 [15] K. Maruhashi, et al., “Design and performance of a Ka-band monolithic phase shifter utilizing nonresonant FET switches,” IEEE Trans. On MTT, August 2000. [16] E. Cohen, S. Ravid, and D. Ritter, “An ultra-low power LNA with 15 dB gain and 4.4 dB NF in 90 nm CMOS foundry for 60 GHz phase array radio,” in Proc. IEEE RFIC Symp., 2008, pp. 61–64. [17] 李威廷,‘‘2.4GHz CMOS單混頻器射頻收發機與5GH功率放大器RFIC及高 Q值螺旋電感之設計研究”,國立成功大學電機工程學系碩士論文,六月,2004年。 [18] S. G. Lee and J.-K. Choi, “Current-reuse bleeding mixer,” IEEE Electronic Letters, vol. 36, no.8, pp. 696-697, Apr. 2000. [19] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw Hill, 2003. [20] D. Ahn, D. W. Kim, and S. Hong, “A K-band high-gain down-conversion mixer in 0.18μm CMOS technology,” IEEE Microwave and Wireless Component Letters, vol. 19, no. 4, pp. 227-229, April 2009. [21] J. Yoon, H. Kim, C. Park, J. Yang, H. Song, S. Lee, and B. Kim, “A new RF CMOS Gilbert mixer with improved noise figure and linearity,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 3, pp. 626-631, Mar. 2008. [22] David M. Pozar, Microwave engineering, Wiley, 2005 [23] 徐邱祥,”磁耦合效應於元件設計及射頻電路應用之研究”, 國立中興大學電機工程學系碩士學位論文,七月,2012年。 [24] 林郁晉,”應用於V頻段無線通訊系統之射頻接收機前端電路設計”, 國立中興大學電機工程學系碩士學位論文,七月,2014年。 [25] 陳崇正,‘‘應用於V頻段無線通訊系統之巴倫器與降頻混頻器設計”, 國立中興大學電機工程學系碩士論文,七月,2013年。 [26] 黃家洋,‘‘應用於無線區域網路802.11a、24GHz與60GHz之射頻接收前端電路設計”,國立中興大學電機工程學系碩士論文,七月,2011年。
摘要: 本論文探討應用於物件偵測雷達系統子電路研發,子電路種類包含V頻段相移器、由低雜訊放大器及混頻器所構成的直接降頻W頻段接收端以及一應用市售調變器晶片與威爾京生功率分波器之專題。本論文自行設計的晶片都是使用TSMC 90nm CMOS製程。論文內容包含元件及電路設計、模擬分析、晶片量測、結果討論。論文整體主軸可分為六個章節:   第一章簡述研究背景,並說明選擇V頻段與W頻段的理由。 第二章對雷達系統子電路作介紹,包含相移器、低雜訊放大器、混頻器的基本概念、以及此三種電路常見的基本架構與各項效能參數。   第三章為應用於V頻段的向量組合式相移器的研究。在此章使用藍基耦合器與平衡轉不平衡轉換器產生I+、I–、Q+、Q–共4個相差90度相位的訊號進入向量組合器進行向量組合,此方式透過電壓控制可以達到360度全相位。晶片總面積為0.732×0.948 mm2,在1.2V的供應電壓之下量測總功耗為27.6 mW。饋入損失依輸出相位不同介於–11.88 dB到–6.63 dB間,P1dB為0 dBm,輸出相位在62.5 GHz到66 GHz誤差在5度內。 第四章為應用於W頻段的直接降頻接收機設計。由一4級的共源極低雜訊放大器及一雙平衡主動混頻器構成。低雜訊放大器使用電晶體並聯及源極退化技巧,後模擬增益為15.59 dB、雜訊指數為6.66dB。混頻器為直接降頻式混頻器,將78 GHz射頻訊號降至基頻,並使用了電流注入技巧。後模擬轉換增益為13.2 dB、雜訊指數為14 dB。接收端整體晶片面積為1.12×0.735 mm2,接收端整體後模擬轉換增益為25.27 dB,雜訊指數為8.17 dB,P1dB為–24dBm,供應電壓1.2V之下功耗為57 mW。 第五章使用一市售調變器晶片及自行佈局的威爾京生功率放大器在印刷電路板上實作一調變電路。在調變器的基頻輸入調頻連續波訊號並將其升頻至12 GHz後由威爾京生功率分波器將訊號分成兩路。 第六章總結各章的研究成果並探討未來的研究方向。
This thesis presents the study of subcircuits for the object-detection radar systems, including a V-band phase shifter, an application of a vendor provided modulator chip with an on-board Wilkinson power divider, and a W-band direct down-conversion receiver which consists of a low noise amplifier (LNA) and a mixer. All of the designed chips in this thesis are implemented in the TSMC 90nm CMOS process. The content of this thesis includes the design of passive devices and circuits, simuation and measurement results, conlusion and discussion. There are 6 chapters in this thesis: Chapter 1 presents the motivation of the study and the benefits of systems implemented in V-band and W-band. Chapter 2 presents the introduction of the subcircuits for radar system, including the phase shifter, the low noise amplifier and the mixer. Furthermore, this chapter presents general considerations in the designs of subcircuits of a radar system, including performance parameters for RF circuits. Chapter 3 shows the design of a V-band vector combination phase shifter. The phase shifter consists of a Lange coupler, 3 balance-to-unbalance converters (Baluns) and a vector combiner. Four signals with 90 degree phase difference, i.e. I+, I–, Q+, and Q– generated by a Lange coupler and two Baluns are input to the vector combiner. Vector combination technique is able to control the output phase by voltage. Continuous phase shift of 360 degree have been measured. The chip area is 0.732×0.948 mm2, and the power comsumption is 27.6 mW under a 1.2V supply. The range of S11 under different control voltage is from –11.88 dB to –6.63 dB. The measured P1dB is 0 dBm. The frequency range for the phase error less than 5 degree is from 62.5 GHz to 66 GHz. Chapter 4 shows the designs of a W-band direct down-conversion receiver, which cosists of a 4-stage common-source low nois amplifier and a double blanced mixer. Parallel-connected transistors and the source degeneration technique are adopted in the proposed LNA. The simulation results of S21 is 15.69 dB while the simulated noise figure is 6.66 dB. The current bleeding technique is adopted in the direct down-conversion mixer. The simulation result of the power conversion gain is 13.2 dB and the simulated noise figure is 14 dB. The whole chip size of the receiver is 1.12×0.735 mm2. The simulated power conversion gain of the receiver chain is 25.27 dB and the noise figure is 8.17 dB at 78 GHz. The 1-dB compression point is –24 dBm. The power comsumption of the proposed W-band receiver is 57 mW under a 1.2V supply. Chapter 5 presents an application of a vendor provided modulator chip and a self-designed Wilkinson divider on a PCB board. The baseband FMCW signal is up-converted to the 12 GHz band by the modulator and its power is divided by the Wilkinson divider for the transmitter and the receiver, respectively. Chapter 6 conludes the thesis and bring a short discussion.
URI: http://hdl.handle.net/11455/96999
文章公開時間: 2019-11-28
Appears in Collections:電機工程學系所

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