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標題: 負電容電晶體之模擬研究:從平面到鰭式結構
Simulation Studies for Negative Capacitance Transistor: From Planar to Fin Structure
作者: 戴易錄
Yi-Lu Dai
關鍵字: 鐵電
次臨界擺幅(Subthreshold Swing)
絕緣層上矽鰭式電晶體(SOI FinFET)
塊材鰭式電晶體(Bulk FinFET)
Negative Capacitance
Subthreshold Swing
Silicon-on-Insulator FinFET(SOI FinFET)
Bulk FinFET
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摘要: 為了克服元件微縮到達物理極限之限制,以具負電容效應之鐵電材料(Ferroelectric, FE)可以解決此一物理極限問題,進而達到次臨界擺幅SS(Subthreshold Swing)可以低于60 mV/dec,並使元件能在較低電壓下達到快速開啟之效果。因此,本論文採用TCAD模擬來研究負電容電晶體元件特性,其所採用之具負電容效應之鐵電材料為HZO,分別應用在三維絕緣層上矽鰭式電晶體(SOI FinFET)和傳統平面MOSFET電晶體上,比較其元件效能差異。我們從HZO的兩組退火溫度條件之實驗結果出發,通過建構數學模型預測其在不同退火溫度條件下,平面與三維結構電晶體元件加了鐵電材料後,其元件特性之變化。從模擬結果來看,「高溫」退火的條件下之HZO其負電容效果較為明顯。研究結果發現HZO的負電容效應在三維SOI FinFET上比傳統平面MOSFET電晶體的效果要更好。此外,本論文所使用的數學模型除了可以預測不同退火溫度下具負電容效應之平面MOSFET與SOI FinFET電晶體的電流-電壓特性外,亦可擴展到其他結構的電晶體,如目前量產之塊材鰭式電晶體(Bulk FinFET)或奈米線(Nanowire)電晶體以及不同之鐵電材料上。
In order to overcome the physical limitation of the device scaling, the ferroelectric (FE) with a negative capacitance effect can be applied to solve this kind of problem, so that Subthreshold Swing (SS) can be lower to 60 mV / dec and the effect of device quick opening can be realized in the low voltage condition. In this thesis, the device characteristics of negative capacitance transistors were studied by TCAD simulation. The adoptive ferroelectric with a negative capacitance effect was HfZrO2, and it was applied to the Silicon-On-Insulator FinFET and planer MOSFET respectively to compare the performance differences of the devices. Then based on the experimental result from the HZO under the two annealing temperature conditions, and mathematical model was applied to forecast the device characteristic changes of SOI FinFET and planer MOSFET with ferroelectric material in different annealing temperatures. According to the simulation results, the negative capacitance effect of HZO was more obvious under a high annealing temperature. It is shown in the research results that the HZO has a better negative capacitance effect when applied to SOI FinFET than to planer MOSFET. In addition, the mathematical model in this thesis not only can be utilized to forecast current-voltage characteristic of SOI FinFET and planer MOSFET with negative capacitance effect under the different annealing temperatures, but also can be used to the transistor with other structures, such as the bulk FinFET, nanowire transistor and other ferroelectric materials.
文章公開時間: 2020-06-06
Appears in Collections:電機工程學系所



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