Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/98222
標題: 應用於內容可定址記憶體之低功率相符線設計
Low Power Match Line Design Used in Content Addressable Memory
作者: 吳桐其
Tung-Chi Wu
關鍵字: 內容可定址記憶體(Content-Addressable-Memory)
三元內容可定址記憶體(Ternary-Content-Addressable-Memory)
轉送表(Forwarding Table)
路由表(Routing Table)
TLB (Translation Lookaside Buffer)
CAM (Content Addressable Memory)
TCAM (Ternary Content Addressable Memory)
Forwarding Table
Routing Table
TLB (Translation Lookaside Buffer)
引用: [1] Yen-Jen Chang, 'Two-Layer Hierarchical Matching Method for Energy-Efficient CAM Design,' IEE Electronics Letters,Vol.43, No. 2, pp. 80-82 , Jan. 2007 [2] Yen-Jen Chang and Yuan-Hong Liao, 'Hybrid-Type CAM Design for Both Power and Performance Efficiency,' IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 16, Issue 8, pp. 965-974 , Aug. 2008 [3] B. Agrawal and T. Sherwood, 'Ternary CAM power and delay model: Extensions and uses,' IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 5, pp. 554–564, May 2008. [4] H. Noda et al., 'A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture,' IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245–253, Jan. 2005. [5] S. Baeg, 'Low-power ternary content-addressable memory design using a segmented match line,' IEEE Trans. Circuits Syst.' I, Reg. Papers, vol. 55, no. 6, pp. 1485–1494, Jul. 2008. [6] J. Zhang, Y. Ye, and B. Liu, 'A current-recycling technique for shadow match-line sensing in content-addressable memories,' IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 6, pp. 677–682, Jun. 2008. [7] C. A. Zukowski and S.-Y. Wang, 'Use of selective precharge for lowpower content-addressable memories,' in Proc. IEEE Int. Symp. Circuits Syst., Jun. 1997, pp. 1788–1791. [8] J. Zhang, Y. Ye, and B. Liu, 'A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs,' in Proc. ACM/IEEE Int. Symp. Low Power Electron. Design, Oct. 2006, pp. 135–138. [9]. Y. Rekhter and T. Li, 'An Architecture for IP Address Allocation with CIDR,' RFC 1518, 1993. [10] D. S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh, and P.T. Balsara, 'Ripple-Precharge TCAM: A Low-Power Solution for Network Search Engines,' International Conference on Computer Design, 2005, pp. 243-248. [11] K. Pagiamtzis and A. Sheikholeslami, 'A Low Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme,' IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, pp. 1512-1519. , Sept. 2004. [12] K. H. Cheng, C. H. Wei, and S. Y. Jiang, 'Static divided word matching line for low-power content addressable memory design,' in Proc. Int. Symp. Circuits Syst., May 2004, pp. 629–632. [13] A. Efthymiou and J. D. Garside, 'An adaptive serial-parallel CAM architecture for low-power cache blocks,' in Proc. Int. Symp. Low Power Electron. Design, 2002, pp. 136–141. [14] B. D. Yang and L. S. Kim, 'A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,' IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1736–1744, Aug. 2005. [15] D. S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh, and P. T. Balsara,'Ripple-precharge TCAM: A low-power solution for network search engines,' in Proc. Int. Conf. Comput. Design, Oct. 2005, pp. 243–248. [16] S.-H. Yang, Y.-J. Hung, and J.-F. Li, 'A low-power ternary content addressable memory with Pai-Sigma matchlines,' IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1909–1913,Oct. 2012. [17] G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, '200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,' in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2003, pp. 387–390. [18] I. Arsovski, T. Chandler, and A. Sheikholeslami, 'A ternary contentaddressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,' IEEE J. Solid-State Circuits, vol. 38,no. 1, pp. 155–158, Jan. 2003. [19] D. Shah and P. Gupta, 'Fast Updating Algorithms for TCAMs,' IEEE Micro, Vol. 21, No. 1, 2001, pp. 36-47. [20] N. Mohan and M. Sachdev, 'Low-capacitance and charge-shared match lines for low-energy high-performance TCAMs,' IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2054–2060, Sep. 2007. [21] H.-Y. Li, C.-C. Chen, J.-S. Wang, and C. Yeh, 'An AND-type matchline scheme for high-performance energy-efficient content addressable memories,' IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1108–1119, May 2006. [22] J.-S. Wang, C.-C. Wang, and C. Yeh, 'TCAM for IP-address lookup using tree-style AND-type match lines and segmented search lines,' in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2006, pp. 577–586. [23].P.-T.Huang, S.-W. Chang, W.-Y. Liu, and W. Hwang, 'Green' microarchitecture and circuit co-design for ternary content addressable memory,' in Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 3322–3325. [24] P.-T. Huang and W. Hwang, 'A 65 nm 0.165 fJ/bit/search 256×144 TCAM macro design for IPv6 lookup tables,' IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 507–519, Feb. 2011. [25] P.-T. Huang, S.-W. Chang, W.-Y. Liu, and W. Hwang, 'A 256×128 energy-efficient TCAM with novel low power schemes,' in Proc. IEEE Int. Symp. VLSI Design, Autom., Test, Apr. 2007, pp. 28–31. [26] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2003. [27] P. Drennan, K. Breen, J. Dyck, and A. Gupta, Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide. New York, NY, USA: Springer-Verlag, 2012. [28] P. T. Huang, S. W. Chang, W. Y. Liu and W. Hwang, 'Green Micro-Architecture and Circuit Co-Design for Ternary Content Addressable Memory,' IEEE International Symposium on Circuits and Systems, 2008, pp. 3322 – 3325 [29] Nitin Mohan and Manoj Sachdev, 'Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs,' IEEE Journal of Solid-State Circuits, Vol. 42, No. 9, pp. 2054-2060, Sep. 2007. [30] Takahito Kusumoto, Daisuke Ogawa, Katsumi Dosaka, Masayuki Miyama, and Yoshio Matsuda, 'A Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications,' in Proc. IEEE Asian Solid-State Circuits Conference, pp.253-256, Nov. 2008. [31] Kun-Lin Tsai, Yen-Jen Chang, and Yu-Cheng Cheng, 'Automatic Charge Balancing Content Addressable Memory with Self-control Mechanism,' IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 10, pp. 2834-2841, Sep. 2014.
摘要: 內容可定址記憶體(Content Addressable Memory,CAM)及三元內容可定址記憶體(Ternary Content Addressable Memory,TCAM)皆應用於快速記憶體內容搜尋,因使用平行比對來實現快速的搜尋,故有著大量功率消耗的問題。本論文分別對CAM及TCAM提出降低ML(Match-Line)上功率消耗的設計,針對CAM部份我們提出MSML(Master-Slave Match Line)主從式ML的設計。藉由結合主從式設計及ML充電準位最小化技術,有效降低ML上的功率消耗。MSML的設計採用主從式ML架構,每列使用1條Master-ML(MML)及N段Slave-ML(SMLs)及1條Final-ML的設計。藉由分享MML與SML上的電荷,能夠將MML充電電壓擺幅最小化,理論上可降低ML上功率消耗達50%以上,根據HSPICE模擬結果,MSML比傳統CAM的設計節省能量消耗達7%~57%。此外進一步改良CAM cell結構以提升搜尋效能,並命名為MSMLhp。在128位元的配置下,MSMLhp比MSML改善EDP(Energy-Eelay Product)達28%,比傳統CAM設計改善EDP效能達到69%。 另外針對TCAM我們提出MAML(Mask-Aware Match-Line)技術,利用prefix 具有don't care連續性的特點,使用分段閘控點方式,在precharge時避免對屬於don't care段的ML充電,以降低ML上的功率消耗。另外因分段的設計,ML上的電壓會被限制在0~Vdd-Vtn之間。與其他相關的研究比較,MAML設計能夠有效的降低ML上的功率消耗,也不需要增加許多複雜的控制電路。MAML使用台積電0.18um製程,容量為256*128-位元,經HSPICE模擬結果顯示,經過改良後的MAML設計,能夠達到最佳的能源及效能上的提升,對比傳統NOR-Type的TCAM設計,在ML上的能量消耗減少約22%~58%。
Content-Addressable Memory (CAM) and Ternary Content-Addressable memory (TCAM) are often used in fast lookup applications. Because using parallel comparisons for fast searching, rsulting in high power consumption. In this paper we propose two ML designs to reduce the ML power consumption of the CAM and TCAM. For the CAM, we propose a new ML architecture, called MSML (Master-Slave Match Line) design, by combining the master-slave ML architecture and charge refill minimization technique to reduce the MLs power dissipated of the CAM. The MSML's ML is composed of one master ML (MML), several slaves ML (SMLs) and one final ML (FML) to perform the search operation. By sharing the MML charge to the SML when mismatched search, our design can minimize the MML charge refill swing, such that the ML power consumption can be reduced effectively. The ML power saving is at least 50%, From the HSPICE simulation, the MSML desing can reduce the ML energy consumption by 7% to 57%. In addition, we further modify the CAM cell structure to improve the search performance of the CAM and called MSMLhp design. In the 128-bit configuration, the MSMLhp improves energy-delay product (EDP) by 28% over MSML design, and improves EDP by 69% compares with the traditional CAM designs. In addition, we propose the MAML (mask-aware match-line) technology for the TCAM ML design. Use the prefix don't care continuity feature, MAML design divides the ML to several segments and adds a gate node(GN) between each ML. Avoiding the no need precharge of MLs to reduce power consumption. Due to the segmentation design, the voltage on the ML will be limited between 0~Vdd-Vtn. Compare with other related research, MAML design can reduce the power consumption effectively on the ML, and without adding many complicated control circuits. MAML uses TSMC's 0.18um process with a capacity of 256*128-bit. The HSPICE simulation results show that the refined MAML design which reduced the ML energy consumption about 22% to 58% compared to the traditional design like NOR-Type TCAM.
URI: http://hdl.handle.net/11455/98222
文章公開時間: 2021-08-22
Appears in Collections:資訊科學與工程學系所

文件中的檔案:

取得全文請前往華藝線上圖書館



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.