Browsing by Author 王行健

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Issue DateTitleAuthor(s)Text
-Built-In-Self-Test and Its Application under High-Level Design王行健-
-Design and Analysis of High-Speed Bus Interface王行健-
-Design and Analysis of Hybrid Concurrent Testing Methods in Fault-Tolerant Systems王行健-
-Distributed diagnosis in multistage interconnection networksWang, S.J.; 王行健-
-High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault TestabilityWang, S.J.; 王行健; Yeh, T.H.-
-Instrumentation Methods for Multiprocessor Systems(I)林偉 ; 王行健-
-Layout-Aware Scan Chain Reorder for Launch-Off-Shift Transition Test CoverageWang, S.J.; 王行健; Peng, K.L.; Hsiao, K.C.; Li, K.S.M.-
-Low-power BIST with a smoother and scan-chain reorder under optimal cluster sizeLai, N.C.; 王行健; Wang, S.J.; Fu, Y.H.-
-Low-power parallel multiplier with column bypassingWen, M.C.; 王行健; Wang, S.J.; Lin, Y.N.-
-Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reductionTsai, P.C.; 王行健; Wang, S.J.-
-RTL Testing for SoC王行健-
-Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing ConstraintWang, S.J.; 王行健; Li, K.S.M.; Chen, S.C.; Shiu, H.Y.; Chu, Y.L.-
-Test and diagnosis of faulty logic blocks in FPGAsWang, S.J.; 王行健; Tsai, T.M.-
-Test data compression for minimum test application timeTsai, P.C.; 王行健; Wang, S.J.; Lin, C.H.-
-Testability improvement by branch point control for conditional statements with multiple branchesWang, S.J.; 王行健; Lien, C.C.-
-Transition Fault Oriented High-Level Test Synthesis王行健-
-一個改變向量種子的技術應用於以線性回饋移位暫存器為基礎的內建式自我測試賴南成 -
-一個無需重新開機的暫存器物理不可複製函數設計練智弘; Chin-Hung Lien
-一整合性高階合成方法:排程與資源配置來達成低功率設計周志霖 ; Chou, Chih-Lin -
-一種使用格雷編碼用以更正多值邏輯快閃記憶體位移錯誤之方法林宏明; Lin, Hung-Ming-