Browsing by Author W. B. Jone

Showing results 1 to 13 of 13
Issue DateTitleAuthor(s)Text
-(IEEE Asian Test Symposium 2000, p299-p303)An Efficient Parallel Transparent Diagnostic BISTD. C. Huang ; W. B. Jone
-(IEEE Instrumentation and Measurement Technology Conference, p601-p606)An Efficient BIST Method for Non-Traditional Faults of Embedded Method ArraysW. B. Jone; D. C. Huang ; S. R. Das-
-(IEEE Instrumentation and Measurement Technology Conference, p700-p705)A Parallel Built-In Self-Diagnostic Method for Non-Traditional Faults of Embedded Memory ArraysV. Arora; W. B. Jone; D. C. Huang ; S. R. Das
-( IEEE Proceedings of the 14th International Conference on VLSI Design, p379-p384)An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory BuffersD. C. Huang ; W. B. Jone; S. R. Das
-(IEEE Proceedings of the 14th International Conference on VLSI Design, p397-p402)A Parallel Built-In Self-Diagnostic Method for Embedded Memory BuffersD. C. Huang ; W. B. Jone; S. R. Das
-(IEEE Proceedings of VLSI Test Symposium, p246-p251)An Efficient BIST Method for Small BuffersW. B. Jone; D. C. Huang ; S. C. Wu; K. J. Lee
-(IEEE Transactions on CAD,21(4):449-465)A Parallel Built-In Self-Diagnostic Method for Embedded Memory ArraysD. C. Huang ; W. B. Jone
-(IEEE Transactions on CAD,21(5):617-628)A Parallel Transparent BIST Method for Embedded Memory Arrays by Tolerating Redundant OperationsD. C. Huang ; W. B. Jone
-(IEEE Transactions on Instrumentation and Measurement,52(5):1381-1390)An efficient BIST method for non-traditional faults of embedded memory arraysW. B. Jone; D. C. Huang ; S. R. Das
-(IEEE Transactions on Instrumentation and Measurement,53(4):915-932)A Parallel Built-In Self-Diagnostic Method for Non-Traditional Faults of Embedded Memory ArraysV. Arora; W. B. Jone; D. C. Huang ; S. R. Das
-(IEEE Transactions on VLSI,10(4):512-515)An Efficient BIST Method for Distributed Small BuffersW. B. Jone; D. C. Huang ; S. C. Wu; K. J. Lee
-(Microprocessor Design Workshop, National Science Council (NSC 98), p083-p089)A Parallel Testing Method for Embedded Small BuffersW. B. Jone; D. C. Huang ; S. C. Wu; K. J. Lee-
-(VLSI Design:An International Journal of Custom-Chip Design,Simulation and Testing,00(0):001-018)Defect Level Estimation for Pseudorandom Testing Using Stochastic AnalysisW. B. Jone; D. C. Huang ; S. C. Chang; S. R. Das