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標題: Effects of Boron Penetration and Poly Gate Depletion on Characteristics of Metal-Oxide-Semiconductor Capacitors
作者: Shih, Yi-Chun
關鍵字: P 通道金屬氧化物半導體電容元件;P-type channel metal-oxide-semiconductor capacitor (PMOS);N通道金屬氧化物半導體電容元件;去耦合電漿氮化;閘極保護層;硼穿透;閘極空乏;N-type channel metal-oxide-semiconductor capacitor (NMOS);Decoupled plasma nitridation (DPN);Gate barrier oxide;Boron penetration;Poly depletion
出版社: 材料科學與工程學系所
引用: [1] G. G. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chappell, J. H. Comfort, B. Davari, R. H. Dennard, R. L. Franch, P. A. McFarland, J. S. Neely, T. H. Ning, M. R. Polcari, and J. D. Warnock, “ A Room Temperature 0.1 um CMOS on SOI,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 41, no. 12, pp. 2405 – 2412 Dec. 1994. [2] K. M. Cham, D. W. Wenocur, J. Lin, C. K. Lau, H. –S. Fu, “ Submicrometer Thin Gate Oxide P-Channel Transistors with P+ Polysilicon Gates for VLSI Applications,” IEEE ELECTRON DEVICE LETTERS, vol. EDL-7, no. 1, pp. 49 – 52 Jan. 1986. [3] M. J. Deen, and Z. X. Yan, “ Substrate Bias Effects on Drain-Induced Barrier Lowering in Short-Channel PMOS Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 37 no. 7, pp. 1707 – 1713 Jul. 1990. [4] R. R. Troutman, “ VLSI Limitations from Drain-Induced Barrier Lowering,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-26, no. 4, pp. 461 – 469 Apr. 1979. [5] A. H. Montree, V. M. H. Meijssen and P. H. Woerlee, “ Comparison of buried and surface channel PMOS devices for low voltage 0.5 um CMOS,” in Proc. VLSI Technology, Systems, and Applications, (VTSA’93), 1993, pp. 11 – 14. [6] N. Lifshitz, “ Dependence of the Work-Function Difference Between the Polysilicon Gate and Silicon Substrate on the Doping Level in Polysilicon,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-32, no. 3, pp. 617 – 621 Mar. 1985. [7] K. S. Krisch, M. L. Green, F. H. Baumann, D. Brasen, L. C. Feldman, and L. Manchanda,“ Thickness Dependence of Boron Penetration Through O2 - and N2O-Grown Gate Oxides and Its Impact on Threshold Voltage Variation,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 43, no. 6, pp. 982 – 990 Jun. 1996. [8] M. -y. Hao, D. Nayak, and R. Rakkhit, “ Impact of Boron Penetration at P+ -poly/Gate Oxide Interface on Deep-Submicron Device Reliability for Dual-Gate CMOS Technologies,” IEEE ELECTRON DEVICE LETTERS, vol. 18, no. 5, pp. 215 – 217 May 1997. [9] C. -Y. Lin, K. -C. Juan, C. -Y. Chang, F.-M. Pan, P.-F. Chou, S. F. Hung, and L.-J. Chen, “ A Comprehensive Study of Suppression of Boron Penetration by Amorphous-Si Gate in P+-Gate PMOS Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 42, no. 12, pp. 2080 – 2088 Dec. 1995. [10] L. K. Han, D. Wristers, J. Yan, M. Bhat, and D. L. Kwong, “ Highly Suppressed Boron Penetration in NO-Nitrided Si02 for p+ -Polysilicon Gated MOS Device Applications,” IEEE ELECTRON DEVICE LETTERS, vol. 16, no. 7, pp. 319 – 321 Jul. 1995. [11] F. Li, S. Mudanai, L. F. Register, and S. K. Banerjee, “ A Physically Based Compact Gate C–V Model for Ultrathin (EOT ~ 1 nm and Below) Gate Dielectric MOS Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 52, no. 6, pp. 1148 – 1158 Jun. 2005. [12] J. M. Sung, C. Y. LU, M. L. Chen, S. J. Hillenius, W. S. Lindenberger, L. Manchanda, T. E. Smith, S. J. Wang, “ Fluorine Effect on Boron Diffusion of P+ Gate Devices,” in Proc. Electron Devices Meeting, 1989, pp. 447 – 450. [13] J. R. PFIESTER, F. K. BAKER, P. J. TOBIN, J. D. HAYDEN, J. W. MILLER, C. D. GUNDERSON, AND L. C. PARRILLO, T. C. MELE, H.-H. TSENG, “ The Effects of Boron Penetration on p+ Polysilicon Gated PMOS Devices,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol 37. no. 8, pp. 1842 – 1851 Aug. 1990. [14] H.-H. Tseng, Y. Jeon, P. Abramowitz, T.-Y. Luo, L. Hebert, J. J. Lee, J. Jiang, P. J. Tobin, G. C. F. Yeap, M. Moosa, J. Alvis, S. G. H. Anderson, N. Cave, T. C. Chua, A. Hegedus, G. Miner, J. Jeon, and A. Sultan, “ Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology,” IEEE ELECTRON DEVICE LETTERS, vol. 23, no. 12, pp. 704 – 706 Dec. 2002. [15] M. Cao, P. V. Voorde, M. Cox, and W. Greene, “Boron Diffusion and Penetration in Ultrathin Oxide with Poly-Si Gate,” IEEE ELECTRON DEVICE LETTERS, vol. 19, no. 8, pp. 291 – 293 Aug. 1998. [16] W. T. Sun, S. H. Chen, C. J. Lin, T. S. Chao, and C. C. -H. Hsu, “ Process Optimization for Preventing Boron-Penetration Using P or As CO-Implant in P-Poly Gate of P-MOSFETs,” in Proc. VLSI Technology, Systems, and Applications, (VTSA’95), 1995, pp. 40 – 43. [17] S. Nygren, D. T. Amm, D. Levy, J. Torres, G. Goltz, T. T. D’ouville, and P. Delpech, “ Dual-Type CMOS Gate Electrodes by Dopant Diffusion from Silicide,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 36. no. 6. pp. 1087 – 1093 Jun. 1989. [18] C. Metzner, A. Kumar, J. Jin, W. Lin, D. Mui, S. Kher, and G.. Higashi, “ Integrating High- K Dielectric Gates In Sub- 65 nm Structures,” Reprinted with permission from Semiconductor Manufacturing Magazine, Nov. 2003, pp. 196 – 201. [19] D. Chong, W. J. Yoo and C. M. Lek, “ Plasma Charging Damage Immunities of Rapid Thermal Nitrided Oxide and Decoupled Plasma Nitrided Oxide,” in Proc. Physical and Failure Analysis of Integrated Circuits, (IPFA’03), Singapore, 7-11 Jul. 2003, pp. 141 – 145. [20] J-L. Everaert, T. Conard, M. Schaekers, “ SiON Gate Dielectric Formation by Rapid Thermal Oxidation of Nitrided Si. ,” in Proc. RTP 2005. 04-07 Oct. 2005, pp. 135 – 138. [21] 余昱穎、陳經緯和簡昭欣,「在具有超薄( EOT=1.6 nm ) 氮化閘極氧化層之0.13 um n 型金氧半電晶體中由熱電子所引發於閘極絕緣層內之電子捕獲現象」,奈米通訊,第十一卷,第四期,第6 – 10頁,2004。 [22] H. Wong, V. A. Gritsenko, “ Dielectric Traps in Amorphous Silicon Oxynitride ,” in Proc. Electron Devices Meeting, 2001, pp. 132 – 139. [23] A. I. Chou, C. Lin, K. Kumar, P. Chowdhury, M. Gardner, M. Gilmer, J. Fulford and J. C. Lee, “ The Effects of Nitrogen Implant into Gate Electrode on the Characteristics of Dual-Gate MOSFETs with Ultra-thin Oxide and Oxynitrides,” in Proc. RELPHY, 1997, pp. 174 – 177. [24] N. H. Kar, L. S. Lai, “ Dual Gate Oxide Formation Using ISSG Selective Oxidation on 2nd Thin Oxide Without Influence on 1st Thick Oxide Thickness,” in Proc. ISSM, 2005, pp. 190 – 192. [25] G. Cellere, M. G. Valentini, M. Caminati, M. E. Vitali, A. Moro, and A. Paccagnella, “ Plasma damage reduction by using ISSG gate oxides,” in Proc. Plasma- and Process-Induced Damage,(PPID’03), 2003, pp. 65 – 68. [26] H. J.L. Forstner, F. Nouri, C. Olsen, “ IN-SITU STEAM GENERATION FOR SHALLOW TRENCH ISOLATION IN SUB-100NM DEVICES,” in Proc. RTP 2003. 23-26 Sept. 2003, pp. 163 – 166. [27] A. Veloso, F. N. Cubaynes, A. Rothschild, S. Mertens, R. Degraeve, R. O’Connor, C. Olsen, L. Date, M. Schaekers, C. Dachs, M. Jurczak, “ Ultra-thin Oxynitride Gate Dielectrics by Pulsed-RF’ DPN for 65 nm General Purpose CMOS Applications,” in Proc. ESSDERC. 2003. 16-18 Sept. 2003, pp. 239 – 242. [28] M. Aoulaiche, M. Houssa, T. Conard, S. D. Gendt, G. Groeseneken, H. E. Maes and M. M. Heyns, “ Postdeposition-Anneal Effect on Negative Bias Temperature Instability in HfSiON Gate Stacks,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 7, no. 1, pp. 146 – 151 Mar. 2007. [29] J. M. McKenna, E. Y. Wu, and S. –H. Lo, “ Tunneling Current Characteristics and Oxide Breakdown in P+ Poly Gate PFET Capacitors,” in Proc. RELPHY.2000. 10-13 Apr. 2000, pp. 16 – 20. [30] C. Subramanian, J. Hayden, W. Taylor, M. Orlowski and T. McNelly, “ Reverse Short Channel Effect and Channel Length Dependence of Boron Penetration in PMOSFETs,” in Proc. IEDM.1995. 10-13 Dec. 1995, pp. 423 – 426. [31] C. – H. Chen, Y. – K. Fang, S. – F. Ting, W. – T. Hsieh, C. – W. Yang, T. – H. Hsu, M. - C. Yu, T. – L. Lee, S. – C. Chen, C. – H. Yu, and M. – S. Liang, “Downscaling Limit of Equivalent Oxide Thickness in Formation of Ultrathin Gate Dielectric by Thermal-Enhanced Remote Plasma Nitridation,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 49, no. 5, pp. 840 – 846 May 2002.
本論文主要探討在P 通道金屬氧化物半導體電容元件(p-type channel metal-oxide-semiconductor capacitor: PMOS capacitor)中使用N 型複晶矽( N+ poly gate ) 與P 型複晶矽( P+ poly gate) 結構與特性的差異,同時針對P 通道金氧半電容元件使用N+ poly gate 結構的埋藏通道與P+ poly gate 結構的表面通道分別作討論,我們發現在使用P+ poly gate 結構的表面通道時,可以利用去耦合電漿氮化(decoupled-plasma-nitridation: DPN)與閘極保護層等製程來減少硼穿透與閘極空乏的現象。
在N 通道金屬氧化物半導體電容元件(n-type channel metal-oxide-semiconductor capacitor: NMOS capacitor) 中,若使用N+ poly gate 結構結合去耦合電漿氮化製程可減少硼離子擴散所造成的臨界電壓偏移,使得N 通道金氧半電容元件的臨界電壓降低,我們針對N+ poly gate 結構的閘極濃度與閘極空乏作研究,並可得出NMOS電容元件的最佳條件。
在P 通道金屬氧化物半導體電容元件使用N+ poly gate 的結構中,當透過植入反轉為P+ poly gate 的摻雜時,我們詳細討論了遭反轉後的表面通道特性,並且利用DPN 製程與閘極保護層製程克服硼穿透與擴散產生的閘極空乏,如此可以平衡硼穿透與閘極空乏效應並減少臨界電壓偏移。
從本論文的研究中可發現當N 型複晶矽閘極使用磷的臨場( in-situ )濃度為2.0×1020 cm-3 ,並且透過P 型閘極摻雜製程,可以使得反轉為P 型複晶矽閘極,而使用DPN 與閘極保護層製程將可使得NMOS電容元件的閘極空乏率低於10% 並減少臨界電壓偏移,而使用DPN 與閘極保護層製程於PMOS電容元件,其中閘極空乏率為27%而且並無硼穿透效應。

關鍵詞: P 通道金屬氧化物半導體電容元件;N通道金屬氧化物半導體電容元件;去耦合電漿氮化;閘極保護層;硼穿透;閘極空乏

This thesis describes the characterization and performance difference of N+ and P+ poly gates in the p-type channel metal-oxide-semiconductor (PMOS) capacitors. A major discussion of this study focuses on the N+ poly gate buried channel and the surface channel in the PMOS capacitors. We also try to reduce the boron penetration and poly depletion by adopting a decoupled-plasma-nitridation (DPN) process and a gate barrier oxide on the P+ poly gate surface channel.
The N+ poly gate combining with the DPN process in n-type channel metal-oxide-semiconductor capacitor can enable the reduction of the threshold voltage shift caused by boron out diffusion. Moreover, it can reduce the threshold voltage shift in n-type channel metal-oxide-semiconductor (NMOS) capacitor. Thus one can probe the optimum process parameters via the dosage of N+ poly gate and poly depletion conditions.
In this thesis, the features of surface channels after inversion is discussed when the PMOS capacitor adopts N+ poly gate to embed inversion as the P+ poly gate dopant. As a result, one can use the DPN process and the gate barrier oxide to overcome either boron penetration or poly depletion caused by the boron ion diffusion and to balance the boron penetration and the poly depletion effect. Furthermore, this can also reduce the threshold voltage shift.
Finally, for the N+ poly gate adopting in-situ phosphorous dosage of 2.01020 cm-3 and enabling the P+ poly gate dopant inversion occur through the P+ pate dopant, the poly depletion rate will be lowered than 10% by using both the DPN process and gate barrier oxide. Besides, it can reduce the threshold voltage shift and leads the poly depletion rate to 27% without the boron penetration effect by adopting the DPN process and the gate barrier oxide in PMOS capacitors.

Keywords: P-type channel metal-oxide-semiconductor capacitor (PMOS)
N-type channel metal-oxide-semiconductor capacitor (NMOS) Decoupled plasma nitridation (DPN)
Gate barrier oxide
Boron penetration
Poly depletion
其他識別: U0005-0507200714200700
Appears in Collections:材料科學與工程學系

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