Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/18987
標題: 現場可程式邏輯陣列內部繞線之測試與診斷
Test and Diagnosis of Interconnect in FPGAs
作者: 黃照能 
Huang, Chao-Neng 
關鍵字: FPGA;現場可程式邏輯陣列;Test;Diagnosis;Interconnect Structure;測試;診斷;內部繞線結構
出版社: 資訊科學學系
摘要: 
現場可程式邏輯陣列(FPGA),FPGA因為擁有下列性質:可重複程式
性與 可重組性,而因為電腦輔助設計流程的高正確度、高效率、和簡便
性,故可用 在雛型生產測試,硬體模擬,及特殊應用積體電路等方面。
使用FPGA可降低成 本,節省上市時間。而由於FPGA內有許多(數千到上
百萬)的可程式元件,在 重譜使用後無可避免地會有部分元件損壞,但
其餘元件仍是可繼續使用的,在 測試之後,我們只要將損壞元件記錄起
來,然後在使用電腦輔助設計工具設計 及重組電路時只程式化沒故障的
邏輯元件即可。而由於FPGA的面積和密度日益 增大以及內部邏輯單元的
增多,我們需要一個有效率且省時省成本的測試方法。
以前對FPGA晶片診斷的研究大多著重在邏輯區塊的錯誤,而發生在
FPGA內部繞線結構上的錯誤未受到重視。在本論文中,對於FPGA內部繞線
結構上的錯誤,我們提出一個測試與診斷的方法。我們發展一組可以定位
出所有單一錯誤和許多多重錯誤的測試集合;此外,其他的多重錯誤也可
運用額外的測試集合找出其位置。

A Field Programmable Gate Array (FPGA) has the following
properties: reprogammability, and reconfigurability.
FPGAs make possible very fast pro- typing and this reduce the
time-to-market. Usually there are many programmablelogics (from
thousands to millions) in FPGAs. It's possible that some logic
will fail after using many times while other componentsstill
work normally. Whenever this is true, all we have to do is
test the FPGA chip and mark bad logic components. So when
users design a circuit using CAD tools,the CAD toolscan bypass
faulty logics during placing androuting (P&R) processes. Because
area and density of FPGAs get largerand larger, an efficient
test method is needed.
Previous researches on diagnosis of FPGAs only deal with faulty
logic blocks,while faults in interconnect structures are largely
ignored. In this paper wepresent a method for the testing and
diagnosis of faults in the interconnect structures of FPGAs.
We develop a predefined set of tests that can locate allsingle
faults and many multiple faults. The remaing multiple faults can
be located with an extra adaptive test set.
URI: http://hdl.handle.net/11455/18987
Appears in Collections:資訊科學與工程學系所

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