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標題: 以內建式自我測試診斷現場可程式邏輯陣列中之連線錯誤
BIST-Based Diagnosis of Interconnect Faults in FPGAs
作者: 李國恩 
Lee, Kuo-En 
關鍵字: FPGA;現場可程式邏輯陣列;BIST;Diagnosis;Interconnect structure;內建式自我測試;診斷;連線結構
出版社: 資訊科學研究所
由於現場可程式邏輯陣列(Field Programmable Gate Array, FPGA)擁有下列性質:可重複程式性與可重組性,使其應用非常廣泛,如:雛型生產測試,硬體模擬,及特殊應用積體電路的設計等方面。使用FPGA的好處可降低電路設計成本,節省上市時間。而由於FPGA內有許多(數千到上百萬)的可程式元件,在重覆使用後無可避免地會有部分元件損壞,但其餘元件仍是可繼續使用的,在測試之後,我們只要將損壞元件記錄起來,然後在使用電腦輔助設計工具設計及重組電路時只程式化沒故障的元件即可。而由於FPGA的面積和密度日益增大以及內部邏輯單元的增多,我們需要一個有效率且省時省成本的測試方法。
使用內建式自我測試 (BIST) 的方法測試FPGA是一個不錯的選擇,因為FPGA的可重複程式性質,在測試之後,測試電路便可移除,因此不需佔用額外的電路面積,也不會降低使用者自定電路的效能。此外,對於測試機器的需求亦較簡單。在這篇論文中我們以內建式自我測試的方法診斷FPGA中的連線錯誤,我們的方法不需假設FPGA內部的CLBs是好的。其次,可完全測試與正確診斷出所有的單一錯誤,而整個測試(診斷)時間僅與FPGA內部的繞線結構有關,而與晶片的面積大小無關

Field Programmable Gate Array (FPGA) has the following properties: reprogrammability, and reconfigurability. Accordingly, FPGAs is used for many applications, for example, fast prototyping, hardware emulation, and ASIC design. Using FPGA for circuit design can reduce the time-to-market and save many costs. Usually there are many (from thousands to millions) programmable components (logic and interconnect) in FPGAs. It's possible that some components will fail after using many times while others still work normally. Whenever this is true, all we have to do is test the FPGA chip and mark bad components. So when users design a circuit using CAD tools, faulty components can be bypassed during placing and routing (P&R) processes. Because area and density of FPGAs get larger and larger, an efficient test method is needed.
Built-In Self-Test for FPGA is attractive, because the testability is achieved without area overhead and performance penalty (after testing, the BIST logic can be removed and reconfigured for its normal operation). Moreover, the requirement for ATE (automatic test equipment) is much simplified. We present a BIST-based diagnosis method for interconnect faults in FPGA. Our BIST approach has no assumption that the CLBs is fault-free. Besides, all single faults can be detected and diagnosed. The total test (diagnosis) time is short and dependent only on the interconnect structure of FPGA, not on FPGA (die) size.
Appears in Collections:資訊科學與工程學系所

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