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標題: 低功率Radix-4布斯乘法器設計
A Low Power Radix-4 Booth Multiplier Design
作者: 劉信均
Liu, Hsin-Chun
關鍵字: 低功率;Shang-Jang Ruan;布斯乘法器;條件式閘控;解碼器;Ing-Chao Lin;Kun-Lin Tsai
出版社: 資訊科學與工程學系所
引用: [1] 崔小平, “基于修正BOOTH編碼的32×32位乘法器”, 電子測量技術, Vol. 30, 2007, pp. 82-85. [2] Gang-Neng Sung, Yan-Jhih Ciou, Chua-Chin Wang, “A Power-Aware 2-Dimensional Bypassing Multiplier Using Cell-Based Design Flow,” IEEE International Symposium on Circuits and Systems (ISCAS ‘08), May 2008, pp. 3338-3341. [3] Jongsu Park, San Kim, Yong-Surk Lee, “A Low-Power Booth Multiplier Using Novel Data Partition Method,” Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (APASIC ‘04), Aug.2004, pp. 54-57. [4] Macsorley, O.L., “High-Speed Arithmetic in Binary Computers,” Proceedings of the IRE, 1961, pp. 67-91. [5] Meng-Lin Hsia, O.T.-C. Chen, “Low-Power Multiplier Optimized by Partial-Product Summation and Adder Cells,” IEEE International Symposium on Circuits and Systems (ISCAS ‘09), May.2009, pp. 3042-3045. [6] Fried, R., “Minimizing energy dissipation in high-speed multipliers,” International Symposium on Low Power Electronics and Design (LPE ‘ 97), Aug.1997, pp. 214-219. [7] Wen-Chang Yeh, Chein-Wei Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, vol. 49, no. 7, Jul.2000, pp. 692-701. [8] Soojin Kim, Kyeongsoon Cho, “Design of High-speed Modified Booth Multipliers Operating at GHz Ranges,” World Academy of Science, Engineering and Technology, 2010. [9] R. Zimmermann, W. Fichtner, “Low-power logic styles:CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, Vol. 32, July 1997, pp. 1079–1090. [10] Andrew D. Booth, “A Signed Binary Multiplication Technique”, The Quaterly Journal of Mechanics and Applied Mathematics, 1951, pp. 236-240. [11] M. D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, Los Altos, CA 94022, USA, 2003. [12] Hsin-Lei Lei, R.C. Chang, Ming-Tsai Chan, “Design of a novel radix-4 booth multipliplier”, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems(APCCAS), 2004, pp. 837-840. [13] Abu-Khater, I.S., Bellaouar, A., Elmasry, M.I., “Circuit techniques for CMOS low-power high-performance multipliers”, IEEE Journal of Solid-State Circuits, 1996, Vol. 31, pp.1535-1546. [14] Cadence Design Systems Inc., “Virtuoso Layout Editor Users Guide-Version 4.4.6. ” June 2000. [15] National Chip Implementation Center,, 2008.
在此篇論文中,我們提出了一種低功率條件式閘控解碼器應用於布斯乘法器上,藉由使用布斯編碼的特性,我們的設計能夠減少一些解碼器中不需要的轉態次數。基於聯電90奈米製程,模擬結果顯示本篇解碼器可以改善動態功率消耗大約11.05個百分比、靜態功率約10.05個百分比。除此之外,應用到32 × 32布斯乘法器則可以達到6.07百分比動態功率與6.48百分比靜態功率的改善效果。

In this paper, we present a low power Booth multiplier with a conditionally gated decoder. Using the features of Booth decoding, our design can reduce the unnecessary node switching in Booth decoder. Based on UMC 90-nm CMOS technology, simulation results show that our decoder can achieve 11.05% improvement in dynamic power consumption and 10.05% in static power consumption. In addition, the power improvement of the 32 32 Booth multiplier can reach 6.07% in dynamic and 6.48% in static after implementing with our decoder.
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