Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/19854
標題: 使用非傳統旁通技術之低功率乘法器設計
Low Power Multiplier with Alternative Bypassing Implementation
作者: 江冠霖 
Jiang, Guan-Lin 
關鍵字: 動態功率;Shanq-Jang Ruan;漏電流功率;乘法器;旁通;浮點問題;Kun-Lin Tsai;Ing-Chao Lin
出版社: 資訊科學與工程學系所
引用: [1] Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits A Design Perspective, second edition, Prentice Hall, 2003 [2] R. Mendoza, A. Ferre, L. Balado, and J. Figueras, “CMOS Leakage Power at Cell Level,” International Conference Design and Test of Integrated Systems in Nanoscale Technology, pp.194, 2006. [3] N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir and N. Vijaykrishnan, “Leakage Current Moore''s Law Meets Static Power,” IEEE Computer, vol. 36, pp.68, 2003. [4] Stephen Brown, Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, third edition, McGraw-Hill, 2009. [5] J. Ohban, V.G. Moshnyaga, and K. Inoue, “Multiplier Energy Reduction Through Bypassing of Partial Products,” Asia-Pacific Conf. on Circuits and Systems. vol.2, pp.13-17, 2002. [6] M. C. Wen, S. J. Wang and Y. M. Lin, “Low Power Parallel Multiplier with Column Bypassing,” IEEE International Symposium on Circuits and Systems, pp.1638-1641, 2005. [7] Y. T. Hwang, J. F. Lin, M. H. Sheu, and C. J. Sheu, “Low Power Multiplier Designs Based on Improved Column Bypassing Schemes,” IEEE Asia Pacific Conference on Circuits and Systems, pp.594-597, 2006. [8] Y. T. Hwang, J. F. Lin, M. H. Sheu, and C. J. Sheu, “Low Power Multipliers Using Enhanced Row Bypassing Schemes,” IEEE Workshop on Signal Processing Systems, pp.136-141, 2007. [9] J. T. Yan, Z. W. Chen, “Low-cost Low-power Bypassing-based Multiplier Design,” IEEE International Symposium on Circuits and Systems, pp.2338-2341, 2010. [10] M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-submicron Cache Memories,” International Symposium on Low Power Electronics and Design, pp.90-95, 2000. [11] S. Mutoh et al., “1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solis-State Circuits, Vol.30, No.8, pp.847-854, 1995. [12] Z. Chen, M. C. Johnson, L. Wei, and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” Proc. Symposium Low Power Design Electron., pp.239-244, 1998. [13] M. Horiguchi, T. Sakata, and K. Itoh, “Switched-source-impedance CMOS Circuit for Low Standby Subthreshold Current Giga-scale LSI''s,” IEEE J. Solid-State Circuits, vol.28, p.1131, 1993. [14] T. Sakurai et al., “Leakage-suppressed Clock-gating Circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for Leakage-dominant Sub-70-nm and Sub-1-V-VDD LSIs,” IEEE Transactions on VLSI Systems, Vol.14, No.4, pp.430-435, 2006. [15] S. H. Kim, V. J. Mooney, “Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design,” IFIP International Conference on Very Large Scale Integration, pp.367-372, 2006. [16] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, “A 3.8-ns CMOS 16×16-b Multiplier Using Complementary Pass-transistor Logic,” IEEE Journal of Solid-State Circuits, pp.388-395, 1990. [17] Cadence Design Systems Inc., “Virtuoso Layout Editor Users Guide-Version 4.4.6.,” June 2000. [18] National Chip Implementation Center, www.cic.org.tw, 2010.
摘要: 
近幾年可攜式裝置越來越熱門,在這些裝置的電路設計當中,降低電路的功率消耗已經成為一個很重要的議題。因為傳統的列旁通乘法器(row-bypassing multiplier)和行旁通乘法器(column-bypassing multiplier)使用到3態緩衝器(tri-state buffers),因而有浮點問題(floating node problem)的發生。而這個問題會使得漏電流功率消耗(leakage power consumption)上升。本篇論文提出一種使用非傳統旁通技術之低功率乘法器設計,其設計優點是不需要使用3態緩衝器(tri-state buffers),以及此乘法器可以使用在列旁通方法(row-bypassing method)的設計上,或行旁通方法(column-bypassing method)的設計上。在實驗上使用聯電90奈米(UMC-90nm)製程,實驗結果顯示,提出的16乘16位元乘法器設計採用行旁通方法(column-bypassing method),可以減少26.9%動態功率消耗以及在平均上可以減少29.96%的漏電流功率消耗。

As portable devices have become increasingly popular, power reduction has become an important issue in device design. Because traditional row-bypassing multipliers and column-bypassing multipliers use tri-state buffers, they suffer from the floating-node problem. This problem in turn increases leakage power consumption. This paper presents a low power multiplier with an alternative design. The advantage of this multiplier design is that it does not use tri-state buffers, and can be used in the row-bypassing method or column-bypassing method. Based on UMC-90nm technology, experimental results show that the proposed 16x16 bit multiplier design with column bypassing method reduces dynamic power by 26.9%, and reduces the leakage power consumption by 29.96% on average.
URI: http://hdl.handle.net/11455/19854
Appears in Collections:資訊科學與工程學系所

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