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標題: 使用非傳統旁通技術之低功率乘法器設計
Low Power Multiplier with Alternative Bypassing Implementation
作者: 江冠霖 
Jiang, Guan-Lin 
關鍵字: 動態功率;Shanq-Jang Ruan;漏電流功率;乘法器;旁通;浮點問題;Kun-Lin Tsai;Ing-Chao Lin
出版社: 資訊科學與工程學系所
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近幾年可攜式裝置越來越熱門,在這些裝置的電路設計當中,降低電路的功率消耗已經成為一個很重要的議題。因為傳統的列旁通乘法器(row-bypassing multiplier)和行旁通乘法器(column-bypassing multiplier)使用到3態緩衝器(tri-state buffers),因而有浮點問題(floating node problem)的發生。而這個問題會使得漏電流功率消耗(leakage power consumption)上升。本篇論文提出一種使用非傳統旁通技術之低功率乘法器設計,其設計優點是不需要使用3態緩衝器(tri-state buffers),以及此乘法器可以使用在列旁通方法(row-bypassing method)的設計上,或行旁通方法(column-bypassing method)的設計上。在實驗上使用聯電90奈米(UMC-90nm)製程,實驗結果顯示,提出的16乘16位元乘法器設計採用行旁通方法(column-bypassing method),可以減少26.9%動態功率消耗以及在平均上可以減少29.96%的漏電流功率消耗。

As portable devices have become increasingly popular, power reduction has become an important issue in device design. Because traditional row-bypassing multipliers and column-bypassing multipliers use tri-state buffers, they suffer from the floating-node problem. This problem in turn increases leakage power consumption. This paper presents a low power multiplier with an alternative design. The advantage of this multiplier design is that it does not use tri-state buffers, and can be used in the row-bypassing method or column-bypassing method. Based on UMC-90nm technology, experimental results show that the proposed 16x16 bit multiplier design with column bypassing method reduces dynamic power by 26.9%, and reduces the leakage power consumption by 29.96% on average.
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