Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/2969
標題: Cyclic digital-to-analog converter with high conversion rate
高轉換速率循環式數位類比轉換器
作者: 林平晉
Lin, Ping-Chin
關鍵字: 循環式;DAC;數位類比轉換器;CDAC
出版社: 光電工程研究所
引用: [1] C. W. Lu and Z. Y. Xu, “A 10-Bit TFT-LCD Column Driver with Hybrid Digital to Analog Converters”, SID 2008 Digest of Tech. Papers, pp. 1394-1397 (2008). [2] Y. J. Jeon, Y. S. Son, J. Y. Jeon, G. H. Lee, H. M. Lee, S. C. Jung, and G. H. Cho, “A Cascaded-Dividing Current DAC with Fine Pitch for High-Resolution AMOLED Display Drivers”, SID 2007 Digest of Tech. Papers, pp. 1644-1646 (2007). [3] B. Greenley, R. Veith, D. Y. Chang, and U. K. Moon, “A Low-Voltage 10-Bit CMOS DAC in 0.01-mm2 Die Area”, IEEE Trans. Circuits System-II: Express Briefs, Volume: 52, pp. 246-250 (2005). [4] P. Rombouts and L. Weyten, “Linearity improvement for the switched capacitor DAC”, Electronics Letters, Volume: 32, pp.293-294 (1996). [5] J. Steensgaard, U. Moon and G. C. Temes, “Mismatch-shaping switching for two capacitor DAC”, Electronics Letters, Volume: 34, pp.1633-1634 (1998). [6] M. J. Bell, “An LCD Column Driver Using a Switch Capacitor DAC”, IEEE J. Solid-State Circuits, Volume: 40, pp.2756-2765 (2005). [7] L. Weyten and S. Audenaert, “Two-capacitor DAC with compensative switching,” Electronics Letters, Volume: 31, pp. 1435-1436 (1995). [8] P. Rombouts, L. Weyten, J. Raman, and S. Audenaert, “Capacitor mismatch compensation for quasi-passive switched-capacitor DAC”, IEEE Trans. Circuits System—I: Analog Digit. Signal Process., Volume:45, pp. 68-71 (1998). [9] H. N. Nguyen, Y. S. Jang, Y. S. Son, S. T. Ryu and S. G. Lee, “A Multi-bit/Cycle 12-bit Cyclic DAC for TFT-LCD Column Drivers”, IDW 2008 Digest of Tech. Papers, pp.1621-1624 (2006). [10] J.H. Kim, B.D. Choi and O.K. Kwon, “1-Bilion-Color TFT-LCD TV with Full HD Format”, IEEE Trans. Consumer Electronics, Volume: 51, pp.1042-1050 (2005). [11] C.D. Go, J.S. Kang, J.H. Kim and O.K. Kwon, “An area efficient true 10-bit source driver for flat panel displays”, IDW 2006 Digest of Tech. Papers, pp.1621-1624 (2006). [12] Y.K. Choi, Z.Y. Wu, K.M. Kim, Y.H. Lee, M.S. Cho, H.S. Kim, D.H Lee and W.G. Chung, “A compact low-power CDAC architecture for mobile TFT-LCD driver ICs”, ISSCC 2008 Digest of Tech. Papers, pp.176-177 (2008). [13] K. Umeda, Y. Hori, and K. Nakajima. “A Novel Linear Digital-to-Analog Converter using Capacitor Coupled Adder for LCD Driver ICs”, SID 2008 Digest of Tech. Papers, pp. 885-888 (2008). [14] Bruce, J.W., “Nyquist-Rate Digital-To-Analog Converter Architectures” Potentials IEEE, Volume: 20 ,pp. 24-28, 2001. [15] Chi-Hung Lin; Bult, K., “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, Solid-State Circuits, IEEE 1998, Digital Object Identifier Page(s): 1948 – 1958. [16] Kati Virtanen,Janne Maunu,Jonne PoikonenmAriPaasio, “A 12-bit Current-Steering DAC with Calibration by Combination Selection” IEEE International Symposium on Circuits and Systems 2007 Page(s): 1469 – 1472. [17] P. Rombouts, L. Weyten, J. Raman, and S. Audenaert, “Capacitor mismatch compensation for quasi-passive switched-capacitor DAC”, IEEE Trans. Circuits System—I: Analog Digit. Signal Process., 45, pp. 68-71 (1998). [18] S. Seki, T. Satio, H. I. Fujishiro, S. Nishi, and Y. Sano, “An 8 bit 1GHz DAC using 0.5u Inverted HEMTs ”, IEEE International Electron Device Meeting, pp.770-773, 1988. [19] 汪芳興,非晶矽薄膜電晶體液晶顯示器驅動積體電路技術,電子月刊,2003年8月第97期,p.98~108。 [20] 戴亞翔,TFT-LCD面板的驅動與設計,五南圖書出版公司,2006年,p.1~260。 [21] 王敏全,「多媒體薄膜電晶體液晶顯示器驅動電路設計」,國立中興大學電機工程學系碩士論文,2005年7月。 [22] 張廷宇,「低溫多晶矽薄膜電晶體液晶顯示器週邊電路設計」,國立中興大學電機工程學系碩士論文,2006年7月。 [23] 楊家銘,「低溫多晶矽薄膜電晶體顯示器驅動電路設計」,國立中興大學電機工程學系碩士論文,2005年6月。 [24] 賴俊睿,「雙倍速循環式數位類比轉換器」,國立中興大學電機工程學系碩士論文,2010年7月。 [25] 劉政杰,「應用於平面顯示器之低偏移電壓緩衝放大器」,國立中興大學電機工程學系碩士論文,2010年7月。
摘要: 
本論文提出一個高轉換速率的循環式數位類比轉換器(cyclic digital-to-analog converter),可用於平面顯示器資料驅動電路(source driving circuit)。
循環式數位類比轉換器採用串列位元輸入,具有結構簡單,不需增加電路元件即可處理任意位元轉換等優點,但缺點是轉換時間會隨位元數增加而增加。
本論文所發表的高轉換速率循環式數位類比轉換器主要的動作原理是使用二個交換電容式雙倍數位類比轉換器來處理十二位元數位訊號,可節省一半的數位類比轉換時間。高轉換速率循環式數位類比轉換器是採用TSMC 0.35-μm CMOS 2P4M製程及VDD為3.3 V的電源電壓下,數位資料訊號輸入頻率為2 MHz,類比電壓輸出頻率為250 KHz,佈局後模擬結果(post-simulation) 顯示,所設計的高轉換速率循環式數位類比轉換器電路平均INL為1.56 LSB,平均DNL為0.0153 LSB,最大INL為4.57 LSB,最大DNL為7.08 LSB,功率消耗為34 μW,佈局面積約為376 μm × 445 μm。

This paper proposed a cyclic digital-to-analog converter with high conversion rate. It can be used for plat panel display data driver circuit.
A cyclic digital-to-analog converter (CDAC) which adopts serial input signal has a simple structure and can convert arbitrary bits. However, its conversion time increases with the increasing input bits.
The proposed cyclic digital-to-analog converter with high conversion rate operation principle was using two improved double-conversion-rate CDAC to separate 12 bit serial data, so it can save half digital to analog conversion time. The proposed CDAC is designed using a TSMC 0.35 μm CMOS technology with a power supply VDD of 3.3V and the input digital data clock is 2 MHz (0.5μs/bit), and the output analog voltage is 250 KHz. The post-simulation results show that the design of the cyclic digital-to-analog converter with high conversion rate average INL is 1.56 LSB, average DNL is 0.0153 LSB, the maximum INL is 4.57LSB, the maximum DNL is 7.08LSB, and power consumption is 34uw, the layout of circuit area about 376 μm × 445 μm.
URI: http://hdl.handle.net/11455/2969
其他識別: U0005-2108201111511400
Appears in Collections:光電工程研究所

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