Please use this identifier to cite or link to this item:
標題: Stress Analysis and Carrier Mobility Calculation of InGaAs MOSFETs
作者: 歐陽湘
Hsiang, Ou-Yang
關鍵字: InGaAs;砷化銦鎵;MOSFETs;Stress Analysis;Carrier Mobility;金氧半場效電晶體;通道應力;遷移率
出版社: 光電工程研究所
引用: [1] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET's with very small physical dimensions,” Proceedings of the IEEE, vol. 87, no. 4, 1999. [2] Donald Cheng, Chichih Liao, K.Y. Cheng, and Milton Feng, “Process development and characteristics of nano III-V MOSFET,” CS MANTECH Conference, April 14-17, 2008. [3] T. W. Kim, D. H. Kim and J. A. del Alamo, “30 nm In0.7Ga0.3As inverted-type HEMTs with reduced gate leakage current for logic applications,” Electron Devices Meeting IEDM 2009 IEEE International, pp. 1-4, 2009. [4] Y. Liu, H. S. Pal, M. S. Lundstrom, D. H. Kim, J. A. del Alamo, and D. A. Antoniadis, “Device physics and performance potential of III-V field-effect transistors,” book chapter in "Fundamental of III-V Semiconductor MOSFETs," S. Oktyabrsky and P. D. Ye (editors), Springer Science, pp. 31-49, 2010. [5] H. C. Chin, X. Gong, X. Liu, and Y. C. Yeo, “Gate influence on the layout sensitivity of Si1−xGex S/D and Si1−yCy S/D transistors including an analytical model,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 10, 2008. [6] W. Walukiewicz, H. E. Ruda, J. Lagowski, and H. C. Gatos, “Electron mobility in modulation-doped heterostructures,” The American Physical Society, vol. 30, pp. 4571-4582, 1984. [7] F. F. Fang, and W. E. Howard, “Negative field-effect mobility on (100) Si surfaces,” Physical Review Letters, vol. 16, No.18, pp. 797-799, 1966. [8] Website of ANSYS: [9] G. Eneman, E. Simoen, P. Verheyen, and K. De Meyer, “Gate influence on the layout sensitivity of Si1−xGex S/D and Si1−yCy S/D transistors including an analytical model,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 55, No. 10, 2008. [10] Peng-Fei Guo, Li-Tao Yang, Yue Yang, Lu Fan, Gen-Quan Han, Ganesh S. Samudra, and Yee-Chia Yeo, “Tunneling feld-effect transistor: effect of strain and temperature on tunneling current,” IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 9, SEPTEMBER 2009. [11] M. H. Lee, S. T. Chang, T.-H.Wu, and W.-N. Tseng, “Driving current enhancement of strained Ge (110) p-Type tunnel FETs and anisotropic effect,” IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 9, 2011. [12] M.H. Lee, B.-F.Hsieh, S.T.Chang, S.W.Lee, "Nickel Schottky junction on epi-Ge for strained Ge metal-oxide-semiconductor field-effect transistors source/drain engineering," accepted by Thin Solid Films, 2011. [13] W.-K. Lin, K.-C. Liu, S.T. Chang, C.-S. Li, "Room temperature fabricated transparent amorphous indium zinc oxide based thin film transistor using high-κ HfO2 as gate insulator," accepted by Thin Solid Films, 2011. [14] C.J. Chiu , Z.W. Pei , S.T. Chang , S.P. Chang , S.J. Chang, "Effect of oxygen partial pressure on electrical characteristics of amorphous indium gallium zinc oxide thin-film transistors fabricated by thermal annealing," Vacuum, Vol.86, pp.246-249, 2011. [15] M. H. Lee, S. T. Chang, B.-F. Hsieh, J.-J. Huang, and C.-C. Lee, “ Analysis and modeling of nano-crystalline silicon TFTs on flexible substrate with mechanical strain,” J. Nanosci. Nanotechnol. Vol.11, pp.10485-10488, 2011. [16] M. H. Lee, B.-F. Hsieh, T.-H. Wu, and S. T. Chang, “P-type tunneling field effect transistors on (100) and (110) orientation Si substrates,” Japanese Journal of Applied Physics, Vol.50, pp.10PC01-10PC01-3, 2011. [17] S. T. Chang, C.-C. Lee, P. H. Sun, “Technology computer-aided design simulation study for a strained InGaAs channel n-type metal-oxide-semiconductor field-effect transistor with a high-k dielectric oxide layer and a metal gate electrode,” Journal of Vacuum Science and Technology B, vol.29, pp.032203-1-5, 2011. [18] B.-F. Hsieh and S. T. Chang, “Subband structure and effective mass of relaxed and strained Ge (110) PMOSFETs,” Solid-State Electronics, Vol.60, pp.37-41, 2011. [19] C.-C. Lee, S. T. Chang, P.-H. Sun, C.-X. Huang, “Impact of strain engineering on nanoscale strained InGaAs MOSFET devices,” Journal of Nanoscience and Nanotechnology, Vol.11, pp.5623-5627, 2011. [20] S.-H. Liao, S. T. Chang, W.-C. Wang, “ Electrical characteristics of Si/SiGe HBTs on Thin-Film SOI substrate,” Journal of the Korean Physical Society, Vol. 57, pp. 1563-1568, 2010. [21] S. T. Chang, P.-H. Sun, C.-C. Lee, “ Impact of strain engineering on InGaAs NMOSFET with a InGaAs alloy stressor,” Thin Solid Films, Vol.519, pp.1738-1742, 2010. [22] M. H. Lee, S.T. Chang, S. Maikap, C.-Y. Peng, and C.-H Lee, “High Ge content of SiGe channel p-MOSFETs on Si (110) surfaces,” IEEE Electron Device Letters, Vol. 31, pp.141-143 , 2010. [23] J. Huang, S. T. Chang, B.-F. Hsieh, M.-H. Liao, W.-C.Wang, and C.-C. Lee, “Strain engineering of nanoscale strained Si MOS devices," Thin Solid Films, Vol.518, pp.S241-S245 January 2010. [24] S. T. Chang, J. Huang, Ming Tang, and C.-Y. Lin, “Effective mass and subband structure of strained Si in PMOS inversion layer with external stress," Thin Solid Films, Vol.518, pp.S154-S158 January 2010. [25] J. Huang, S. T. Chang, W.-C. Wang, and C.-C. Lee,“Simulation of a nanoscale strained Si NMOSFET with a silicon-carbon alloy stressor," Thin Solid Films, Vol.518, pp.S72-S75 January 2010.(Impact factor 1.909, 3/18) [26] S. T. Chang, W.-C. Wang, C.-C. Lee, and J. Huang, “A TCAD simulation study of impact of strain engineering on nanoscale strained Si NMOSFETs with a silicon-carbon alloy stressor,” Thin Solid Films, Vol.518, pp.1595-1598 December 2009. [27] M.H. Lee, S.T. Chang, S. Maikap, C.-F. Huang, “The role of carbon on performance of strained-Si:C surface channel NMOSFETs,” Solid State Electronics, Vol.52, pp.1569-1572, 2008. [28] M. H. Lee, S. T. Chang, B. F. Hsieh , C.-Y. Peng, S. Maikap, and S.-H. Liao, “Studying the impact of carbon on device performance for strained-Si MOSFETs,” Thin Solid Films, Vol.517, pp.105-109, 2008. [29] S.T. Chang, S.H. Liao, C.-Y. Lin, “The impact of uniaxial stress on subband structure and mobility of strain Si NMOSFETs,” Thin Solid Films, Vol.517, pp.356-358, 2008. [30] M. H. Lee, S. T. Chang, S. W. Lee, P. S. Chen, K.-W. Shen, and W.-C. Wang, “Strained-Si with carbon incorporation MOSFETs for Source/Drain engineering,” Applied Surface Science, Vol.254, pp.6147-6150, 2008. [31] M. H. Lee, S. T. Chang, S. Maikap, K.-W. Shen and W.-C. Wang, “Short channel effect improved strained-Si:C-Source/Drain PMOSFETs,” Applied Surface Science, Vol.254, pp.6144-6146, 2008. [32] S. T. Chang, C.-Y. Lin, S. H. Liao, “Theoretical study of electron mobility for Silicon-Carbon alloys,” Applied Surface Science, Vol.254, pp.6203-6207, 2008. [33] Y.-J. Yang, W. S. Ho, C.-F. Huang, S. T. Chang, and C. W. Liu, “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect-transistors,” Applied Phys. Lett., Vol.91, pp.102103-1-3 ,2007. [34] S. Maikap, M. H. Lee, S. T. Chang, and C.W. Liu, “Characteristics of strained-germanium p- and n-channel field effect transistors on Si (111) substrate,” Semiconductor Science and Technology, Vol.22, pp.342-347, 2007. [35] S. T. Chang, H.-S. Tsai, and C.Y. Kung, “Strained Si channel NMOSFETs using a stress with Si1-yCy Source and Drain stressors,” Thin Solid Films, Vol.508, pp.333-337, 2006.
三五族半導體是極具潛力的材料,將有機會取代矽用於未來的CMOS技術。最近,具源/汲極應力源之應變InGaAs n型金氧半場效電晶體也被首次驗證其可行性。在本論文中,我們將透過應力模擬及遷移率計算研究應變InGaAs金氧半場效電晶體的效能。
本論文的內容安排如下: 首先,我們先在第一章介紹三五族材料及電晶體元件的進展。然後,在第二章會說明InGaAs場效電晶體反轉層的電子遷移率計算的方法。接著在第三章會報告我們對n型與p型InGaAs場效電晶體的應力模擬。在第四章,我們提出一個新的通道應力解析解可適用於InGaAs場效電晶體。最後一章則是結論。

III-V materials will be the potential candidates to replace Si in the future CMOS technology. Recently, the strained InGaAs n-MOSFET with S/D Stressors was demonstrated for the first time. In this thesis, we will study the performance of strained InGaAs MOSFETs with S/D Stressor using stress simulation and mobility calculation. This thesis is organized as following: First, we will briefly introduce the overview of III-V materials and transistors in Chapter 1. Electron mobility calculation for InGaAs MOSFET will be given in Chapter 2. Stress simulations for n-MOSFET and p-MOSFET are studied in Chapter 3. In Chapter 4, we propose a new analytical model for channel stress in InGaAs MOSFET with S/D Stressors. Finally, the summary will be concluded in Chapter 5.
其他識別: U0005-2406201223475900
Appears in Collections:光電工程研究所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.