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作者: 賴俊睿
Lai, Chun-Jui
關鍵字: 數位類比轉換器;digital-to-analog converter (DAC);循環式;雙倍速;交換電容;cyclic;double conversion rate;capacitor swapping
出版社: 光電工程研究所
引用: [1] M. Lee, Y. S. Son, Y. J. Jeon, J. Y. Jeon, S. C. Jung, and G. H. Cho.“Area and power efficient 10-bit column driver with interpolating DAC and push-pull amplifier for AMLCDs”, SID 2008 Digest of Tech. Papers, pp.889-891 (2008). [2] C. W. Lu and Z. Y. Xu, “A 10-Bit TFT-LCD Column Driver with Hybrid Digital to Analog Converters”, SID 2008 Digest of Tech. Papers, pp. 1394-1397 (2008). [3] Y. J. Jeon, Y. S. Son, J. Y. Jeon, G. H. Lee, H. M. Lee, S. C. Jung, and G. H. Cho, “A Cascaded-Dividing Current DAC with Fine Pitch for High-Resolution AMOLED Display Drivers”, SID 2007 Digest of Tech. Papers, pp. 1644-1646 (2007). [4] B. Greenley, R. Veith, D. Y. Chang, and U. K. Moon, “A Low-Voltage 10-Bit CMOS DAC in 0.01-mm2 Die Area”, IEEE Trans. Circuits System-II: Express Briefs, 52, pp. 246-250 (2005). [5] P. Rombouts and L. Weyten, “Linearity improvement for the switched capacitor DAC”, Electronics Letters, 32, pp.293-294 (1996). [6] J. Steensgaard, U. Moon and G. C. Temes, “Mismatch-shaping switching for two capacitor DAC”, Electronics Letters, 34, pp.1633-1634 (1998). [7] M. J. Bell, “An LCD Column Driver Using a Switch Capacitor DAC”, IEEE J. Solid-State Circuits, 40, pp.2756-2765 (2005). [8] L. Weyten and S. Audenaert, “Two-capacitor DAC with compensative switching,” Electronics Letters, 31, pp. 1435-1436 (1995). [9] P. Rombouts, L. Weyten, J. Raman, and S. Audenaert, “Capacitor mismatch compensation for quasi-passive switched-capacitor DAC”, IEEE Trans. Circuits System—I: Analog Digit. Signal Process., 45, pp. 68-71 (1998). [10] H. N. Nguyen, Y. S. Jang, Y. S. Son, S. T. Ryu and S. G. Lee, “A Multi-bit/Cycle 12-bit Cyclic DAC for TFT-LCD Column Drivers”, IDW 2008 Digest of Tech. Papers, pp.1621-1624 (2006). [11] J.H. Kim, B.D. Choi and O.K. Kwon, “1-Bilion-Color TFT-LCD TV with Full HD Format”, IEEE Trans. Consumer Electronics, 51, pp.1042-1050 (2005). [12] C.D. Go, J.S. Kang, J.H. Kim and O.K. Kwon, “An area efficient true 10-bit source driver for flat panel displays”, IDW 2006 Digest of Tech. Papers, pp.1621-1624 (2006). [13] Y.K. Choi, Z.Y. Wu, K.M. Kim, Y.H. Lee, M.S. Cho, H.S. Kim, D.H Lee and W.G. Chung, “A compact low-power CDAC architecture for mobile TFT-LCD driver ICs”, ISSCC 2008 Digest of Tech. Papers, pp.176-177 (2008). [14] K. Umeda, Y. Hori, and K. Nakajima. “A Novel Linear Digital-to-Analog Converter using Capacitor Coupled Adder for LCD Driver ICs”, SID 2008 Digest of Tech. Papers, pp. 885-888 (2008). [15] Bruce, J.W., “Nyquist-Rate Digital-To-Analog Converter Architectures” Potentials IEEE, Volume: 20 ,pp. 24-28, 2001. [16] Chi-Hung Lin; Bult, K., “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, Solid-State Circuits, IEEE 1998, Digital Object Identifier Page(s): 1948 – 1958. [17] Kati Virtanen,Janne Maunu,Jonne PoikonenmAriPaasio, “A 12-bit Current-Steering DAC with Calibration by Combination Selection” IEEE International Symposium on Circuits and Systems 2007. [18] P. Rombouts, L. Weyten, J. Raman, and S. Audenaert, “Capacitor mismatch compensation for quasi-passive switched-capacitor DAC”, IEEE Trans. Circuits System—I: Analog Digit. Signal Process., 45, pp. 68-71 (1998). [19] 汪芳興,非晶矽薄膜電晶體液晶顯示器驅動積體電路技術,電子月刊,2003年8月第97期。 [20] 戴亞翔,TFT-LCD面板的驅動與設計,五南圖書出版公司,2006年,p.1~260。 [21] 王敏全,多媒體薄膜電晶體液晶顯示器驅動電路設計,國立中興大學電機工程學系碩士論文,2005年7月。 [22] 張廷宇,低溫多晶矽薄膜電晶體液晶顯示器週邊電路設計,國立中興大學電機工程學系碩士論文,2006年7月。 [23] 楊家銘,「低溫多晶矽薄膜便晶體顯示器驅動電路設計」,國立中興大學電機工程學系碩士論文,2005年6月。
循環式數位類比轉換器(cyclic digital-to-analog converter)採用串列位元輸入,具有結構簡單,不需增加電路元件即可處理任意位元轉換等優點,但缺點是轉換時間會隨位元數增加而增加。在以往的研究中,有人提出雙倍速循環式數位類比轉換器,採用四個電容,可同時輸入高位元及低位元的數位訊號,使傳統循環式數位類比轉換器的訊號輸入時間減為原來的一半,但缺點是電容面積將倍增。

本論文之數位類比轉換器以TSMC 0.35-μm CMOS 3.3 V製程來設計,佈局後模擬(post-simulation) 顯示,交換電容式改良型雙倍速循環式數位類比轉換器最大積分線性誤差(INL)為 0.76 LSB,最大微分非線性誤差(DNL)為0.8 LSB,符合小於 1 LSB之規格。

A cyclic digital-to-analog converter (CDAC) which adopts serial input signal has a simple structure and can convert arbitrary bits. However, its conversion time increases with the increasing input bits. In previous studies, one has presented that the double-conversion-rate CDAC, which uses four capacitors can input the most-significant bit (MSB) and the least-significant bit simultaneously. However, the capacitor area of the double-conversion-rate CDAC is doubled as compared to the traditional one.
This paper presents an improved double-conversion-rate CDAC, which contains only three capacitors. The proposed circuit can sample input data and share charges at the same phase clock, so its conversion rate is also about two times of the traditional CDAC. Comparing with double-conversion-rate CDAC, The proposed circuit needs fewer capacitors and adopts capacitor swapping technique, thereby reducing chip area and improving nonlinearity errors of the DAC. Simulation results show that under the condition of 0.1% of capacitive mismatching, the nonlinearity error of the proposed CDAC with capacitor swapping is reduced to below one-tenth of that without capacitor swapping
The proposed CDAC is designed using a TSMC 0.35 μm CMOS technology with a power supply of 3.3V. The post-simulation results show that the maximum INL and DNL of the CDAC with capacitor swapping are 0.76 and 0.8 LSB, respectively. They conform to the specification of 1 LSB.
其他識別: U0005-2308201011585500
Appears in Collections:光電工程研究所

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