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Study on the Degradation Mechanism of P-type Low Temperature Poly-Si Thin Film Transistors under AC Stress
|關鍵字:||低溫複晶矽;Low Temperature Poly-Si;薄膜電晶體;交流應力;可靠度;熱載子效應;自發熱效應;Thin-Film Transistors;AC Stress;Reliability;Hot Carrier Effect;Self-Heating Effect||出版社:||光電工程研究所||引用:|| H. Kawamoto “The History of Liquid-Crystal Displays”, Proc. IEEE, vol. 90, pp. 460-500, (2002).  C.T. Liu, “Revolution of the TFT LCD Technology”, J. Display Technol., vol. 3, pp. 342-350, (2007).  M. Petouris, A. Kalantzopoulos and E. Zigouris “An FPGA-Based Digital Camera System Controlled from an LCD Touch Pannel”, Circuits and Systems, doi：10.1109/ ISSCS.2009.5206086, (2009).  Y.-T. Chiu, C.-T. Chen, Y.-C Chang, J.-T, Yeh “A Transparent Electrets Loudspeaker for a LCD Monitor”, Electrets, doi：10.1109/ ISE.2011.6085059, (2011).  S. W. Lee “Intelligent Liquid Crystal Display (i-LCD) for Next Generation Television Application”, IEEE Trans. on Consumer Electronics, vol. 53, pp. 1247-1253, (2007).  D. Murley, N. Young, M. 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Low temperature poly-Si thin film transistors (LTPS TFTs) have attracted much attention in recent years because the carrier mobility is several orders of magnitude higher than amorphous silicon TFTs. Howerver, in driving circuits, P-type poly-Si TFTs are subjected dynamic pulses in the gate and source terminals. Therefore, it’s very important to investigate the dagradation of LTPS TFTs under the AC signal stress. The previos reports focus on the degradation of LTPS TFTs under dynamic gate stress; however, there are few works concentrating on the P-type LTPS TFTs with the dynamic stress on the source. Thus, in this thesis, the hot-carrier effect induced by the gate pulse stress and the self-heating effect insuced by the source pulse stress are investigated
In the first part, DC hot-carrier effect would cause increased mobility, positive shifted threshold voltage and reduced leakage current. The degradation mechanism was channel carriers were exposed to high lateral electric field and attained higher energy to become hot carriers, and then induced impact ionization near the drain junction and electron-hole pairs were generated. The impact generated electrons would be injected into oxide or semiconductor/SiO2 interface and attracted the holes to accumulate near the drain side. In this situation, the effective channel length was shortened, and the accumulated holes were similar to lightly doped region to reduce leakage current effectively. Then the device stressed under gate pulse between its ON and OFF region was investigated, and the electrical degradation of device was similar to DC hot-carrier effect. According to the experiment, the numbers of pulse repetition dominated the degradation of device. The dynamic degradation model is proposed. When the gate voltage swept from -18V to VTP, the holes gathered and formed the channel. When the gate voltage charged from VTP to +18V, the holes were swept to the source or the drain depending on the Fermi energy level at the SiO2/poly-Si interface. The hot holes would cause impact ionization near the drain and source junctions, and then the generated electrons would be injected into oxide or semiconductor/SiO2 interface because of the voltage difference between the gate and source or the gate and drain. It would induce tht channel shortening effect.
In the second part, DC self-heating effect would cause decreased mobility, negative shifted threshold voltage and decreased on current. The degradation mechanism was the high vertical electric field between the gate and source would accelerate the carriers and the hot holes would gain energy to break Si-Si or Si-H bonds at semiconductor/SiO2 interface, causing the increase of the defect states. Then rectangular pulse signals, dynamically sweeping from -18V to 18V, were applied to the source terminal and both the gate and drain ones were grounded. The degradation of the device was the same as the DC self-heating effect. To indentify the main degraded duration, the AC signal was divided into the positive pulse signal and the negative pulse signal, and it was obvious that the device was degraded at the positive pulse signal. Based on the experiment results, the device was degraded seriously when the signal frequency was decreased and the duty cycle was increased. Therefore, the device’s degradation was strongly dependent on the duration of the hole injection. The duration was longer, the probability of the holes which gained sufficient energy to inject into oxide and created the density of the defects was higher. To further verify the generation of trap states was near the source side, we used FR-IV measurement method. The result was very clear that the on current in case of forward measurement was smaller than in case of reverse measurement. Besides, the C-V relationships were examined and there were two degradation mechanisms for the poly-Si TFTs with bias stressing, which were charge trapping and interface state creation. We distinguished them with the power-law mode.
Based on the results, when the pulse signals were applied to the source terminal, it’s very important to shorten the duration of hole injection by increasing the frequency and decreasing the duty cycle to enhance the reliability of P-type LTPS TFTs.
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