Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/2988
標題: P型低溫複晶矽薄膜電晶體操作在交流訊號下退化機制之研究
Study on the Degradation Mechanism of P-type Low Temperature Poly-Si Thin Film Transistors under AC Stress
作者: 詹博鈞
Chan, Po-Chun
關鍵字: 低溫複晶矽;Low Temperature Poly-Si;薄膜電晶體;交流應力;可靠度;熱載子效應;自發熱效應;Thin-Film Transistors;AC Stress;Reliability;Hot Carrier Effect;Self-Heating Effect
出版社: 光電工程研究所
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摘要: 
P型低溫複晶矽薄膜電晶體已被廣泛討論,因為它比非晶矽薄膜電晶體擁有更高的載子遷移率。然而做為驅動電路時,薄膜電晶體在閘極與源極端都將承受交流訊號,因此對於低溫複晶矽薄膜電晶體,在交流訊號下可靠度的探討是非常重要的。之前已有許多文獻研究,於閘極端給予交流訊號下的退化現象,但較少文獻對於P型低溫複晶矽薄膜電晶體,於源極端給予交流訊號的衰退機制做探討。故本篇論文對於交流訊號加於閘極端引發的熱載子效應,與交流訊號加於源極端導致的自發熱效應之退化現象做更深入的研究。

在第一部分中,P型元件在直流熱載子應力測試條件下,載子的遷移率增加、臨界電壓正偏移且漏電流降低。其退化機制最主要是,通道載子在傳遞電荷時,因較大橫向電場而獲得能量形成熱載子,並在靠近汲極端的空乏區發生離子化撞擊而產生電子電洞對。離子化撞擊產生的電子,因垂直電場而被注入氧化層或氧化層與半導體介面中,因正負電荷相吸,使累積在下方的電洞如同輕摻雜汲極,因此使漏電流降低且有效通道長度縮短。在閘極端給予交流訊號,使元件伴隨在導通區域與關閉區域的應力測試實驗,電性上的衰退與直流訊號相似。從實驗結果中可發現,脈衝波的振盪次數主導了元件的衰退。其暫態退化機制是當閘極電壓從-18V到臨界電壓時,電洞聚集在通道中。但當閘極電壓從臨界電壓到+18V時,通道層必須即刻消失,因此電洞將因能帶的分佈,被掃入汲極與源極端,而造成離子化撞擊並產生電洞電子對。電子因閘極-汲極與閘極-源極存在壓差所形成的電場,而被注入至氧化層或氧化層與半導體介面中,導致有效通道長度的縮減。

在第二部分中,元件在直流自發熱應力測試條件下,載子的遷移率下降、臨界電壓負偏移且導通電流下降。其退化機制最主要是,通道在傳遞電洞的過程中,因較大垂直電場的加速而被注入氧化層或氧化層與半導體介面中,使矽氫鍵斷裂造成介面態增加。在源極端給予-18V~+18V脈衝波且閘極與汲極同時接地的應力測試,發現元件在電性上的衰退與直流自發熱應力測試相同。為了要區分元件的衰退區段,將-18V~+18V的交流訊號分為正交流訊號與負交流訊號。由實驗結果可知,元件電性在正交流訊號下有明顯的衰退,且當頻率越低或是工作週期越長時,電性的退化更為顯著。我們推測元件的退化與高電位持續的時間有強相關,當高電位持續時間越長,電洞因縱向電場的加速而被注入至氧化層或氧化層與半導體介面中的機率也越高,使缺陷增加。為了證明此項論點,利用順向-反向電流-電壓量測結果可知,順向量測下的導通電流值,明顯低於反向量測的導通電流值,此意味著缺陷產生的區域在靠近源極端。除此之外,利用電容-電壓的檢測可發現,電荷的被捕陷與介面態的產生皆會導致元件電性的衰退,我們使用了Power law模型來做辨別。

由研究的結果可知,要提高P型低溫複晶矽薄膜電晶體的可靠度,對於源極端給予交流訊號的應力條件,需增加操作頻率與減少工作週期來縮短電洞被注入氧化層的持續時間。

Low temperature poly-Si thin film transistors (LTPS TFTs) have attracted much attention in recent years because the carrier mobility is several orders of magnitude higher than amorphous silicon TFTs. Howerver, in driving circuits, P-type poly-Si TFTs are subjected dynamic pulses in the gate and source terminals. Therefore, it’s very important to investigate the dagradation of LTPS TFTs under the AC signal stress. The previos reports focus on the degradation of LTPS TFTs under dynamic gate stress; however, there are few works concentrating on the P-type LTPS TFTs with the dynamic stress on the source. Thus, in this thesis, the hot-carrier effect induced by the gate pulse stress and the self-heating effect insuced by the source pulse stress are investigated

In the first part, DC hot-carrier effect would cause increased mobility, positive shifted threshold voltage and reduced leakage current. The degradation mechanism was channel carriers were exposed to high lateral electric field and attained higher energy to become hot carriers, and then induced impact ionization near the drain junction and electron-hole pairs were generated. The impact generated electrons would be injected into oxide or semiconductor/SiO2 interface and attracted the holes to accumulate near the drain side. In this situation, the effective channel length was shortened, and the accumulated holes were similar to lightly doped region to reduce leakage current effectively. Then the device stressed under gate pulse between its ON and OFF region was investigated, and the electrical degradation of device was similar to DC hot-carrier effect. According to the experiment, the numbers of pulse repetition dominated the degradation of device. The dynamic degradation model is proposed. When the gate voltage swept from -18V to VTP, the holes gathered and formed the channel. When the gate voltage charged from VTP to +18V, the holes were swept to the source or the drain depending on the Fermi energy level at the SiO2/poly-Si interface. The hot holes would cause impact ionization near the drain and source junctions, and then the generated electrons would be injected into oxide or semiconductor/SiO2 interface because of the voltage difference between the gate and source or the gate and drain. It would induce tht channel shortening effect.

In the second part, DC self-heating effect would cause decreased mobility, negative shifted threshold voltage and decreased on current. The degradation mechanism was the high vertical electric field between the gate and source would accelerate the carriers and the hot holes would gain energy to break Si-Si or Si-H bonds at semiconductor/SiO2 interface, causing the increase of the defect states. Then rectangular pulse signals, dynamically sweeping from -18V to 18V, were applied to the source terminal and both the gate and drain ones were grounded. The degradation of the device was the same as the DC self-heating effect. To indentify the main degraded duration, the AC signal was divided into the positive pulse signal and the negative pulse signal, and it was obvious that the device was degraded at the positive pulse signal. Based on the experiment results, the device was degraded seriously when the signal frequency was decreased and the duty cycle was increased. Therefore, the device’s degradation was strongly dependent on the duration of the hole injection. The duration was longer, the probability of the holes which gained sufficient energy to inject into oxide and created the density of the defects was higher. To further verify the generation of trap states was near the source side, we used FR-IV measurement method. The result was very clear that the on current in case of forward measurement was smaller than in case of reverse measurement. Besides, the C-V relationships were examined and there were two degradation mechanisms for the poly-Si TFTs with bias stressing, which were charge trapping and interface state creation. We distinguished them with the power-law mode.

Based on the results, when the pulse signals were applied to the source terminal, it’s very important to shorten the duration of hole injection by increasing the frequency and decreasing the duty cycle to enhance the reliability of P-type LTPS TFTs.
URI: http://hdl.handle.net/11455/2988
其他識別: U0005-2307201211420900
Appears in Collections:光電工程研究所

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