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dc.contributorShu-Tong Changen_US
dc.contributor.authorHuang, Jun-Haoen_US
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dc.description.abstract本文研究的主要重點為N型通道的低溫多晶矽薄膜電晶體(LTPS TFTs)在不同的通道方向上對於電性會有什麼影響。首先我們閱讀文獻吸取相關知識,並且介紹TFT的相關知識背景以及製程技術,也簡介一些降低晶界缺陷的方法。我們分成兩個部分來完成研究。 第一個部份我們實際量測(100)wafer的LTPS N-TFTs 來觀察通道方向與電性的關係並且定義一些所使用到的電性參數,藉由ID-VG與ID-VD的量測結果發現本文LTPS N-TFTs的導通電流大小隨著通道的角度上下起伏,0度時最低,在通道方向為45度時有最大的導通電流以及最高的載子遷移率,而在90度時又掉了下去。 第二個部份藉由Sentaurus TCAD模擬軟體去擬合量測出來的數值,建立一個trap model去描述晶粒中的trap濃度分佈。由模擬結果發現造成通道方向對電性影響的主因為不同通道方向載子所看到的trap濃度不一,導致導通電流有不一樣的變化。zh_TW
dc.description.abstractThe present study focuses on the relationship between low temperature poly-Si thin film transistor (LTPS N-TFTs) channel direction and carrier mobility. First, we study related knowledge from the literature as well as introduce the background and process technology regarding thin film transistors. We also introduce the reduction of the grain boundary defect. Our study is broken down into two steps. The first step, we observe the relationship between LTPS N-TFTs and its electron characteristics. Then, we define some electron parameters that we want to know. From the ID-VG and ID-VD measurement results, we show that the drain current of LTPS N-TFTs will be an up- and down-swing curve. The smallest current occurs while the channel direction is equal to 0�. When the channel direction is equal to 45�, it has the largest drain current and the highest carrier mobility. Additionally, the drain current is reduced again at the channel direction when it is equal to 90�. The second step, we fit the measured result with a Sentaurus TCAD to simulate its electron characteristics. We establish a trap model to help us describe its grain trap state. As a result, the different channel directions have different trap state influences on carrier mobility that results in different drain currents.en_US
dc.description.tableofcontents誌謝辭 i 中文摘要 iii Abstract iv 目錄 v 圖目錄 vii 表目錄 xi 第一章 簡介 1 1.1 研究背景與動機 1 1.2 低溫多晶矽 1 1.3未來展望:應用於有機發光二極體 3 第二章LTPS TFT元件製程 4 2.1 TFT元件簡介 4 2.2 LTPS結晶方式 4 2.2.2 準分子雷射結晶法 (ELC) 5 2.2.3 金屬側向誘發結晶法 6 2.3 LTPS元件之結構與製程 6 2.4 結晶晶粒(grain) 9 2.4.1 氫化反應(Hydrogenation) 10 2.4.2 氧電漿處理(Oxygen Plasma Treatment) 11 2.4.3 水蒸氣熱處理(H2O Vapor Heat Treatment) 12 第三章LTPS TFT元件電性量測 13 3.1 I-V量測方法 13 3.1.1 ID-VG量測 13 3.1.2 ID-VD量測 13 3.2 量測儀器與軟體之佈置簡介 13 3.3 電腦量測軟體參數設定 15 3.4 電晶體參數計算 18 3.4.1 載子遷移率(μ)與轉移電導(transconductance, Gm)定義 18 3.4.2 臨界電壓(VTN)之定義 19 3.4.3 導通電流(Ion)之定義 19 3.4.4 漏電流(Ioff)之定義 19 3.5 量測結果討論與分析 20 3.5.1 通道方向與各電性參數之關係 23 3.6 量測實驗結果補充 27 第四章LTPS TFT元件TCAD模擬 30 4.1 多晶矽TFTs之物理機制 30 4.2 多晶矽載子傳輸的電子模型 31 4.2.1 Seto’s 模型假設 31 4.2.2 Seto’s model修正:Mandurah 假設 33 4.2.3 晶界狀態密度 33 4.3 模擬結果 36 4.3.1 Trap Model 38 4.3.2元件模擬trap濃度分佈 40 4.4 不同通道方向模擬結果比較 45 第五章 總結與未來展望 48 5.1總結 48 5.2 未來展望 49zh_TW
dc.titleElectrical Measurement and TCAD Simulation for LTPS Thin Film Transistoren_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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