Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/2995
DC FieldValueLanguage
dc.contributor張書通zh_TW
dc.contributorShu-Tong Changen_US
dc.contributor.author黃鈞顥zh_TW
dc.contributor.authorHuang, Jun-Haoen_US
dc.contributor.other光電工程研究所zh_TW
dc.date2013en_US
dc.date.accessioned2014-06-06T05:24:47Z-
dc.date.available2014-06-06T05:24:47Z-
dc.identifierU0005-2207201314194000en_US
dc.identifier.citation[1] 陳志強編著,LTPS低溫複晶矽顯示器技術,全華科技圖書股份有限公司, pp. 2-1,2-2,2-7。 [2] 工業技術研究院 胡國仁 LTPS LCD Process 報告,(2010)。 [3] Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi “Impact of Channel Direction Dependent Low Field Hole Mobility on (100) Orientation Silicon Surface”, Japanese Journal of Applied Physics 50, doi:10.1143/JJAP.50.04DC03, (2011). [4] Tejas Krishnamohan, Donghyun Kim, Thanh Viet Dinh, Anh-tuan Pham, Bernd Meinerzhagen, Christoph Jungenmann, Krishna Saraswat “Comparison of (001), (110) and (111) Uniaxial-and Biaxial-Strained-Ge and Strained-Si PMOS DGFETs for All Channel orientation:Mobility Enhancement, Drive Current, Delay and Off-State Leakage”, IEDM 2008, pp.1-4, (2008). [5] Y. Li, K. F. Lee, I.H. Lo, C. H. Chiang and K.Y. Huang “Dynamic Characteristic Optimization of 14 a-Si:H TFTs Gate Driver Circuit Using Evolutionary Methodology for Display Panel Manufacturing”, J. Display Technol, vol.5, pp.274-280, (2011). [6] M. Karayama, K. Nakazawa, Y. Kanemori, M. Katagami, Y.Kanatani, K.Yano, M. Hijigawa “A 10.4 In.-Diagonal Full-Color TFT-LCD with New Self-Aligned a-Si TFTs for OHP System”, Display Research Conference, doi:10.1109/DISPL.1991.167480, (1991). [7] M. Yuki, K. Masumo, S. Takafuji, T. Asakawa, N. Imajyo and M. Kunigita “A full Color LCD Addressed by Poly Si TFTs fabricated at Low Temperature below 450 Degrees C”, Display Research Conference, doi:10.1109/DISPL.1988.11315, (1988). [8] A. Mimura, N. Konishi, K.Ono, J.I. Ohwada, Y.Hosokawa, Y.A. Ono, T. Suzuki, K. Miyata and H. Kawakami “High Performance Low-Temperature Poly-Si n-Channel TFTs for LCD”, IEEE Electron Device Letters, vol.36, pp.351-359, (1989). [9] O. Kunz, Z. Ouyang, J. Wong and A. G. Alberle “Device Fabrication Scheme for Evaporated SPC Poly-Si Thin-Film Solar Cells on Glass(EVA)”, Optoelectronic and Microelectronic Materials and Devices, doi:10.1109/COMMAD.2008.4802149,(2008). [10] Y. Tao, S. Varlamov, J. Wong, O. Kunz and R. Egan “Effects of SPC Temperature on Properties of Evaporated Poly-Si Thin Films and Solar Cells”, Photovoltaic Specialists Conference, doi:10.1109/PVSC.2010.5646847, (2010). [11] T. Sameshima, M. Hare and S. Usui “XeCl Excimer Leaser Annealing Used to Fabricate Poly-Si TFTs”, Jpn. J. Appl. Phys., vol.28 pp.1789-1793 (1989). [12] S. W. Lee and S. K. Joo “Temperature Poly-Si Thin-Film Transistor Fabrication by Metal-Induced Lateral Crystallization”, IEEE Electron Device Letters, vol. 17, pp. 160-162 (1996). [13] D. Murley, N. Young, M. Traninor and D.McCulloch “An Investigation of Laser Annealed and Metal-Induced Crystallized Polycrystalline Silicon Thin-Film Transistors”, IEEE Electron Device Letters, vol. 48, pp.1145-1151 (2001). [14] M. Wang, Z. Meng, Y. Zohar and M. Wong “Metal-Induced Laterally Crystallized Polycrystalline Silicon for Integrated Sensor Application”, IEEE Electron Device Letters, vol.48, pp.794-800 (2001). [15] C. Hu, M. Wang, M. Zhang, B. Zhang and M. Wong “Degradation of Solution Based Metal Induced Laterally Crystallized P-type Poly-Si TFTs under DC Bias Stresses”, Reliability Physics Symposium, doi:10.1109/RELPHY.2008.4558913, (2008). [16] Donald Neamen “An Introduction to Semiconductor Devices”, McGraw-Hill international edition. [17] H. Lhermite, “Modelisation mono- et bidimensionnelle des phenomenes electrostatiques dans le silicium polycristallin petits grains. Application a l’effect de champ dans une structure M.O.S. ,” Thesis of University of Rennes 1, n°193, (1988). [18] M. Shur, Physics of Semiconductor Devices, New Jersey:Prentice Hall, Inc., (1990). [19] K. Lee, M. Shur, T. A. Fjeldly and T. Ytterdal, Semiconductor Device Modeling for VLSI, Prentice-Hall, (1993). [20] T. A. Fjeldly, T. Ytterdal and M. Shur, Introduction to Device Modeling and Circuit Simulation, New York:John Wiley&Sons,(1998). [21] B. Iniguez, T. A. Fjeldly, T. Ytterdal and M. Shur, “Thin Film Transistor Modeling,” Silicon and Beyond:Advance Device Models and Circuit Simulations, World Scientific, Singapore, 33-54, (2000). [22] M. Jacunski, M. Shur, and M. Hack, “Threshold voltage, field-effect mobility, and gate-to-channel capacitance in polysilicon TFTs,” IEEE Trans. Electron Devices, 43, 1433 (1996). [23] J. Levinson et al., “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., 53, 1193-1202(1982). [24] J. G. Fossum, A. Ortiz-Conde, H. Schichijo, and S. K. Banerjee, “Effects of grain boundaries on the channel conductor of SOI MOSFETs,” IEEE Trans. Electron Device, 30, 933-940 (1983). [25] G.-Y. Yang, S.-H. Hur, and C.-H. Han, “A Physical-Based Analytical Turn-On Model of Polysilicon Thin-Film Transistor for Circuit Simulation,” IEEE Trans. Electron Devices, 46(1), 165-172 (1999). [26] S.-W. Lee, B.-I. Lee, T.-H. Ihn, T. Kim, Y.-T. Kang, and S.-K. Joo, ”Device characteristics of a poly-silicon thin-film transistor fabricated by MILC at low temperature,” in Proc. Flat Panel Display Materials II Symp., 195-200, (1997). [27] G. A. Bhat, Z. Jin, H. S. Kwok, and M. Wong, “Effects of Longitudinal Grain Boundaries on the Performance of MILC-TFTs,” IEEE Electron Device Letters, 20(2), 97-99 (1999). [28] Y. Tsunoda, T. Sameshima, S. Higashi, “Defect reduction technologies of polycrystalline silicon thin film transistors,” Proc. Fifth Symp. Thin Film Transistor Technologies, Y. Kuo, Ed., Electrochemical Society, Penning, New Jersey, 2001, p.229. [29] Y. Tsunoda, T. Sameshima, S. Higashi, ”Improvement of Electrical Properties of Pulsed Laser Crystallized Silicon Films by Oxygen Plasma Treatment,” Jpn. J. Appl. Phys.,39,1656 (2000). [30] T. Sameshima, M. Satoh, K. Sakamoto, A. Hisamatsu, K. Ozaki and K. Saitoh, “Heat Treatment of Amorphous and Polycrystalline Silicon Thin Film with H2O Vapor,” Jpn. J. Appl. Phys., 37, L112-L114 (1998). [31] K. Asada, K. Sakamoto, T. Watanable, T. Sameshima and S. Higashi, “Heat treatment with High-Pressure H2O Vapor of Pulsed Laser Crystallized Silicon Films,” Jpn. J. Appl. Phys.,39,3883 (2000). [32] S. Higashi, D. Abe, Y. Hiroshima, K. Miyashita, T. Kawamura, S. Inoue, and T. Shimoda, “High-Quality SiO2/Si interface formation and its application to fabrication of low-temperature-processed polycrystalline Si thin-film transistor,” Jpn. J. Appl. Phys., 41 3646 (2002). [33] Edited by Yue Kuo,” Thin Film Transistors Materials and Processes, Volume2 Polycrystalline Silicon Thin Film Transistors.”en_US
dc.identifier.urihttp://hdl.handle.net/11455/2995-
dc.description.abstract本文研究的主要重點為N型通道的低溫多晶矽薄膜電晶體(LTPS TFTs)在不同的通道方向上對於電性會有什麼影響。首先我們閱讀文獻吸取相關知識,並且介紹TFT的相關知識背景以及製程技術,也簡介一些降低晶界缺陷的方法。我們分成兩個部分來完成研究。 第一個部份我們實際量測(100)wafer的LTPS N-TFTs 來觀察通道方向與電性的關係並且定義一些所使用到的電性參數,藉由ID-VG與ID-VD的量測結果發現本文LTPS N-TFTs的導通電流大小隨著通道的角度上下起伏,0度時最低,在通道方向為45度時有最大的導通電流以及最高的載子遷移率,而在90度時又掉了下去。 第二個部份藉由Sentaurus TCAD模擬軟體去擬合量測出來的數值,建立一個trap model去描述晶粒中的trap濃度分佈。由模擬結果發現造成通道方向對電性影響的主因為不同通道方向載子所看到的trap濃度不一,導致導通電流有不一樣的變化。zh_TW
dc.description.abstractThe present study focuses on the relationship between low temperature poly-Si thin film transistor (LTPS N-TFTs) channel direction and carrier mobility. First, we study related knowledge from the literature as well as introduce the background and process technology regarding thin film transistors. We also introduce the reduction of the grain boundary defect. Our study is broken down into two steps. The first step, we observe the relationship between LTPS N-TFTs and its electron characteristics. Then, we define some electron parameters that we want to know. From the ID-VG and ID-VD measurement results, we show that the drain current of LTPS N-TFTs will be an up- and down-swing curve. The smallest current occurs while the channel direction is equal to 0�. When the channel direction is equal to 45�, it has the largest drain current and the highest carrier mobility. Additionally, the drain current is reduced again at the channel direction when it is equal to 90�. The second step, we fit the measured result with a Sentaurus TCAD to simulate its electron characteristics. We establish a trap model to help us describe its grain trap state. As a result, the different channel directions have different trap state influences on carrier mobility that results in different drain currents.en_US
dc.description.tableofcontents誌謝辭 i 中文摘要 iii Abstract iv 目錄 v 圖目錄 vii 表目錄 xi 第一章 簡介 1 1.1 研究背景與動機 1 1.2 低溫多晶矽 1 1.3未來展望:應用於有機發光二極體 3 第二章LTPS TFT元件製程 4 2.1 TFT元件簡介 4 2.2 LTPS結晶方式 4 2.2.2 準分子雷射結晶法 (ELC) 5 2.2.3 金屬側向誘發結晶法 6 2.3 LTPS元件之結構與製程 6 2.4 結晶晶粒(grain) 9 2.4.1 氫化反應(Hydrogenation) 10 2.4.2 氧電漿處理(Oxygen Plasma Treatment) 11 2.4.3 水蒸氣熱處理(H2O Vapor Heat Treatment) 12 第三章LTPS TFT元件電性量測 13 3.1 I-V量測方法 13 3.1.1 ID-VG量測 13 3.1.2 ID-VD量測 13 3.2 量測儀器與軟體之佈置簡介 13 3.3 電腦量測軟體參數設定 15 3.4 電晶體參數計算 18 3.4.1 載子遷移率(μ)與轉移電導(transconductance, Gm)定義 18 3.4.2 臨界電壓(VTN)之定義 19 3.4.3 導通電流(Ion)之定義 19 3.4.4 漏電流(Ioff)之定義 19 3.5 量測結果討論與分析 20 3.5.1 通道方向與各電性參數之關係 23 3.6 量測實驗結果補充 27 第四章LTPS TFT元件TCAD模擬 30 4.1 多晶矽TFTs之物理機制 30 4.2 多晶矽載子傳輸的電子模型 31 4.2.1 Seto’s 模型假設 31 4.2.2 Seto’s model修正:Mandurah 假設 33 4.2.3 晶界狀態密度 33 4.3 模擬結果 36 4.3.1 Trap Model 38 4.3.2元件模擬trap濃度分佈 40 4.4 不同通道方向模擬結果比較 45 第五章 總結與未來展望 48 5.1總結 48 5.2 未來展望 49zh_TW
dc.language.isozh_TWen_US
dc.publisher光電工程研究所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2207201314194000en_US
dc.subject半導體zh_TW
dc.subjectsemiconductoren_US
dc.subject低溫多晶矽薄膜電晶體zh_TW
dc.subject量測zh_TW
dc.subjectLTPSen_US
dc.subjectmesurementen_US
dc.title低溫多晶矽薄膜電晶體之電性量測與模擬zh_TW
dc.titleElectrical Measurement and TCAD Simulation for LTPS Thin Film Transistoren_US
dc.typeThesis and Dissertationzh_TW
item.languageiso639-1zh_TW-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
Appears in Collections:光電工程研究所
Show simple item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.