Please use this identifier to cite or link to this item:
標題: 填充矽通孔之新穎電鍍鎳鎢合金配方
A Novel Nickel-Tungsten Alloy Plating Formula for Filling Through Silicon Vias
作者: 黃馨嫚
Huang, Hsin-Man
關鍵字: 填充矽通孔;Through Silicon Vias;合金電鍍;鎳鎢合金;Nickel-Tungsten Alloys
出版社: 化學工程學系所
引用: 第 8 章 參考文獻 1 T. R. Rosebrugh and W. L. Miller, “Mathematical Theory of the Change of Concentration at the Electrode, Brought about by Diffusion and by Chemical Reaction”, J. Phys. Chem., 14, 816, 1910. 2 J. J. Sun, K. Kondo, T, Okamura, S. Oh, M. Tomisaka, H, Yonemura, M. Hoshion, and K. Takahashi, “High-Aspect-Ratio Copper Via Filling Used for Three Dimensional Chip Stacking”, J. Electrochem. Soc., 150, 355, 2003. 3 K. Kondo, T. Yonezawa, D. Mikami, T. Okubo, Y. Taguchi, K. Takahashi, and D. P. Barkey, “High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking”, J. Electrochem. Soc., 152, H173, 2000. 4 N. V. Mandich, “Pulse and Pulse-Reverse Electroplating”, Met. Finish., 98, 374, 2000. 5 L. Xu, P. Dixit, J. Miao, and J. H. L. Pang.“Through-Wafer Electroplated Copper Interconnect with Ultrafine Grains and High Density of Nanotwins”, Appl. Phys. Lett., 90, 033111, 2007. 6 胡啟章,“電化學原理與方法”,五南圖書出版股份有限公司,2002年。 7 H. Xiao, “Introduction of Semiconductor Manufacturing Technology”, Prentice-Hall Inc., New Jersey, 2001. 8 張勁燕,“VLSI概論”,五南圖書出版股份有限公司,2008年。 9 P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, “Damascene Copper Electroplating for Chip Interconnections”, IBM J. Res. & Develop., 42, 567, 1998. 10 羅正忠、張鼎張,“半導體製程技術導論”,台灣培生教育出版股份有限公司,2009年。 11 T. B. Massalski, “Binary Alloy Phase Diagrams”, ASM International, Material Park, OH, p.2703, 1990. 12 C. S. Shin, Y. W. Kim, D. Gall, J. E. Greene, and I. Petrov, “Phase Composition and Microstructure of Polycrystalline and Epitaxial TaNx Layers Grown on 103 Oxidized Si(001) and MgO(001) by Reactive Magnetron Sputter Deposition”, Thin Solid Film, 402, 172, 2002. 13 O. Luhn, C. V. Hoof, W. Ruythooren, and J.-P. Celis, “Barrier and Seed Layer Coverage in 3D Structures with Different Aspect Ratios using Sputtering and ALD Processes”, Microelectron. Eng., 85, 1947, 2008. 14 S. B. Antonelli, T. L. Allen, D. C. Johnson, and V. M. Dubin, “Crystallization Behavior of Ni-P Alloy Films on Co and Cu Seed Layers”, J. Electrochem. Soc., 152, J120, 2005. 15 T. Osaka, N. Takano, T. Kurokawa, T. Kaneko, and K. Ueno, “Electroless Nickel Ternary Alloy Deposition on SiO2 for Application to Diffusion Barrier Layer in Copper Interconnect Technology”, J. Electrochem. Soc., 149, C573, 2002. 16 V. Dubin, Y. Shacham-Diamand, B. Zhao, and P.K. Vasudev, “Simulation of Electroless Deposition of Cu Thin Films for Very Large Scale Integration Metallization”, J. Electrochem. Soc., 144, 898, 1997. 17 E. Rudnik and J. Gorgosz, “The Influence of Maleic Acid on the Co–P Electroless Deposition”, Surf. Coat. Technol., 201, 6953, 2007. 18 Y. Shacham-Diamand, A. Zylberman, N. Petrov, and Y. Sverdlov, “Electroless Co(Mo,P) Films for Cu Interconnect Application”, Microelectron. Eng., 64, 315, 2002. 19 Y. Sverdlov, V. Bogush, H. Einati, and Y. Shacham-Diamand, “Electrochemical Study of the Electroless Deposition of Co (W,B) Alloy”, J. Electrochem. Soc., 152, C631, 2005. 20 H. Nakano, T. Itabashi, and H. Akahoshi, “Electroless Deposited Cobalt-Tungsten-Boron Capping Barrier Metal on Damascene Copper Interconnection”, J. Electrochem. Soc., 149, C573, 2002. 21 柯賢文,“表面與薄膜處理技術”,全華科技圖書,2005 年。 22 V. M. Dubin, Y. Shacam-Diamand, B Zhao, P. K. Vasuder, and C. H. Ting, “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc, 144, 898, 1997. 104 23 S. K. Ryu, T. Jiang, K. H. Lu, J. Im, H. Y. Son, K. Y. Byun, R. Huang, and P. S. Ho, “Characterization of Thermal Stresses in Through-Silicon Vias for Three-Dimensional Interconnects by Bending Beam Technique”, Appl. Phys. Lett., 100, 041901, 2012. 24 L. W. Kong, A. C. Rudack, P. Krueger, E. Zschech, S. Arkalgud, and A. C. Diebold, “3D-Interconnect:Visualization of Extrusion and Voids Induced in Copper-Filled Through-Silicon Vias (TSVs) at Various Temperatures using X-Ray Microscopy”, Microelectron. Eng., 92, 24, 2012. 25 S. H. Choa, C. G. Song, and H. S. Lee, “Investigation of Durability of TSV Interconnect by Numerical Thermal Fatigue Analysis”, Int. J. Precis. Eng. Man., 12, 589, 2011. 26 E. J. Cheng and Y. L. Shen, “Thermal Expansion Behavior of Through-Silicon- Via Structures in Three-Dimensional Microelectronic Packaing”, Microelectron. Reliab., 52, 534, 2012. 27 K. Zeng, R. Stierman, T. C. Chiu, D. Edwards, K. Ano, and K. N. Tu, “Kirkendall Void Formation in Eutectic SnPb Solder Joints on Bare Cu and Its Effect on Joint Reliability”, J. Appl. Phys., 97, 024508, 2005. 28 P. P. Bhattacharjee, R. K. Ray, and A. Upadhyaya, “Nickel Base Substrate Tapes for Coated Superconductor Applications”, J. Mater. Sci., 42, 1984, 2007. 29 G. A. Dosovitskiy, S. V. Samoilenkov, A. R. Kaul, and D. P. Rodionov, “Thermal Expansion of Ni-W, Ni-Cr, and Ni-Cr-W Alloys Between Room Temperature and 800℃”, Int. J. Thermophys, 30, 1931, 2009. 30 S. I. Simak, A. V. Ruban, and Y. H. Vekilov, “Thermodynamic, Mechanical and Thermal Properties of Ni-W Alloys from Harris Functional LMTO-CPA Calculations”, Solid State Commun., 87, 393, 1993. 31 楊聰仁,“無電鍍鎳及其應用”,國璋出版社,1987年。 32 張宏祥、王為,“電鍍工藝學”,天津科技出版社,2008年。 33 N. V. Parthasaradhy, “Practical Electroplating Handbook”, Prentice-Hall, 1989. 34 C. H. Huang, “Hydrolysis of Sulfamate Ion in Nickel Sulfamate Solution”, Plat. 105 Surf. Finish., 81, 64, 1994. 35 Y. M. Lin and S. Chern, “Effect of Additives and Chelating Agents on Eletroless Copper Plating”, Appl. Surf. Sci., 178, 116, 2001. 36 A. Brenner, “Electrodeposition of Alloys”, Vol. I & II, Academic Press, New York, 1963. 37 S. O. Moussa, M. A. M. Ibrahim, and S. S. A. E. Rehim, “Induced Electrodeposition of Tungsten with Nickel from Acidic Citrate Electrolyte”, J. Appl. Electrochem., 36, 333, 2006. 38 R. M. Krishnan, C. J. Kennedy, S. Jayakrishnan, S. Sriveeraraghavan, S. R. Natarajan, and P. G. Venkatakrishnan, “Electrodeposition of Nickel-Tungsten Alloys”, Met. Finish., 93, 33, 1995. 39 陳黼澤、黃大展、林招松、潘永寧,“電鍍鎳鎢合金之微結構與機械性質 ”, 中正領學報,第39卷,第一期,2010年。 40 N. Eliaz and E. Gileadi, “The Mechanism of Induced Codeposition of Ni-W Alloys”, ECS Trans., 2, 337, 2007. 41 O. Younes and E. Gileadi, “Electroplating of Ni/W Alloys”, J. Electrochem. Soc., 149, C100, 2002. 42 N. Eliaz and E. Gileadi, “Induced Codeposition of Alloys of Tungsten, Molybdenum and Rhenium with Transition Metals”, Modern Aspects of Electrochemistry, 2008. 43 張凱程,“氨基磺酸鎳電鍍槽參數測試”,2009年。 44 G. P. Xiang, “Theory and Practice of Reverse pulse current Electroplating”, Tianjin Science-Technology press, 1989. 45 K. C. Chan, N. S. Qu, and D. Zhu, “Effect of Reverse Pulse Current on the Internal Stress of Electroformed Nickel”, J. Mater. Process. Tech., 63, 819, 1997. 46 I. Mizushima, P. T. Tang, H. N. Hansen, and M. A.J. Somers, “Development of a New Electroplating Process for Ni-W Alloy Deposits”, Electrochim. Acta, 51, 888, 2005. 47 I. Mizushima, P. T. Tang, H. N. Hansen, and M. A.J. Somers, “Residual Stress in 106 Ni-W Electrodeposits”, Electrochim. Acta, 51, 6128, 2006. 48 H. Cesiulis, A. Baltutiene, M. Donten, M. L. Donten, and Z. Stojek, “Increase in Rate of Electrodeposition and in Ni(II) Concentration in the Bath as a Way to Control Grain Size of Amorphous/Nanocrystalline Ni-W alloys”, J. Solid State Electrochem., 6, 237, 2002. 49 M. Donten, Z. Stojek, and H. Cesiulis, “Formation of Nanofibers in Thin Layers of Amorphous W Alloys with Ni, Co, and Fe Obtained by Electrodeposition”, J. Electrochem. Soc., 150, C95, 2003. 50 O. Younes-Metzler, L. Zhu, and E. Gileadi, “The Anomalous Codeposition of Tungsten in The Presence of Nickel”, Electrochim. Acta, 48, 2551, 2003. 51 O. Younes and E. Gileadi, “Electroplating of High Tungsten Content Ni/W Alloys”, Electrochem. Solid-State Lett., 3, 543, 2000. 52 侯俊宇,“應用趨力有限,3D IC”,新通訊元件雜誌,第109期,2010年。 53 鍾文仁、陳佑任,“IC封裝製程與CAE應用”,全華科技圖書股份有限公司,2005年。 54 L. W. Schaper, S. L.Burkett, S. Spesshoefer, G. V. Vangara, Z. Rahman, and S. Polamreddy, “Architectural Implications and Process Development of 3-D VLSI Z-Axis Interconnect Using Through Silicon Vias”, IEEE., 28, 356, 2005. 55 S. L. Burkett, X. Qiao, D. Temple, B. Stoner, and G. McGuire, “Advanced Processing Technique for Though-Wafer Interconnects”, J. Vac. Sci. Technol. B, 22, 248, 2004. 56 A. Elpida, “Akita Elpida Memory Successfully Develops World’s Thinnest 1.4mm MCP with 20 Stacked Dies”, News Release, 2007. 57 T. Semiconductor, “Interconnected Wafer Stack”, Wafer stacking technology, 2003. 58 R. Beica, P. Siblerud, C. Sharbono, and M. Bernt, “Advanced Metallization for 3D Integration”, IEEE., 212, 2008. 59 N. T. Nguyen, E Boellaard, N. P. Pham, V. G. Kutchoukov, G. Craciun, and P. M. Sarro, “Through-Wafer Copper Electroplating for Three-Dimensional 107 Interconnects”, J Micromech. Microeng., 12, 395, 2002. 60 X. Zhang, TC Chai, J. H. Lau, C. S. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, GY Tang, YY Ong, SR Vempati, E. Wai, HY Li, EB Liao, N. Ranganathan, V. Kripesh, J. Sun, J. Doricko, and C. J. Vath, “Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA Package”, IEEE., 305, 2009. 61 P. Garrou, “How Might 3D ICs Come Together ”, Semiconductor International, 2008. 62 汪建民, “材料分析”,第三版,第五章,中國材料科學學會,2011年。 63 羅吉宗,“薄膜科技與應用”,全華圖書,2005年。 64 林昆明,“金相試片製備顯微組織觀察與分析”,材料基礎實驗,2003年。 65 張立,“微結構分析與電子顯微鏡學”,材料與社會雜誌,第37期,1990年。 66 柯志忠,“以原子層沉積製程成長氧化物薄膜與金屬奈米顆粒及其應用”, 國 家實驗研究院儀器科技研究中心,2007年。 67 蕭建男,“奈米結構原子級薄膜製程技術”,國家實驗研究院儀器科技研究中 心簡訊,第84期,2007年。 68 C. H. Lee, J. E. Bonevich, U. Bertocci, K. L. Steffens, and T. P. Moffat, “Superconformal Ni Electrodeposition Using 2-Mercaptobenzimidazole”, J. Electrochem. Soc., 158, D366, 2011. 69 C. H. Lee, J. E. Bonevich, J. E. Davies, and T. P. Moffat, “Superconformal Electrodeposition of Co and Co-Fe Alloys Using 2-Mercapto-5-benzimidazole- sulfonic Acid”, J. Electrochem. Soc., 156, D301, 2009. 70 S.-K. Kim, J. E. Bonevich, D. Josell, and T.P. Moffat, “Electrodeposition of Ni in Submicrometer Trenches”, J. Electrochem. Soc., 154, D443, 2007. 71 朱立群,“實用電鍍故障分析與處理技術”,國防工業出版社,2007年。 72 C. H. Lee, J. E. Bonevich, J. E. Davies, and T. P. Moffat, “Magnetic Materials for Three-Dimensional Damascene Metallization : Void-Free Electrodeposition of Ni an Ni70Fe30 Using 2-Mercapto-5-benzimidazolesulfonic Acid”, J. Electrochem. Soc., 155, D499, 2008. 108 73 W. P. Dow, H. S. Huang, M. Y. Yen, and H. C.Huang, “Influence of Convection Dependent Adsorption of Additives on Microvia Filling by Copper Electroplating”, J. Electrochem. Soc., 152, C425, 2005. 74 O. Luhn, J. P. Celis , C. V. Hoof , K. Baert, and W. Ruythooren, “Leveling of Microvias by Electroplating for Wafer-Level-Packaging”, ECS Trans., 6, 123, 2007. 75 M. Yokoi, S. Konishi, and T. Hayaashi, “Adsorption Behavior of Polyoxyenthyleneglycol on the Copper Surface in an Acid Copper Sulphate Bath”, Denki Kagaku, 52, 218, 1984. 76 W. P. Dow, M. Y. Yen, W. B. Lin, and S. W. Ho, “Influence of Molecular Weight of Polyethylene Glycol on Microvia Filling By Copper Electroplating”, J. Electrochem. Soc., 152, C769, 2005.

Three-dimensional (3D) chip stacking is a major focus in recent research and development of microelectronics, MEMS, and MOEMS technology. Through silicon vias (TSV) play a key role in IC chip stacking connections. A main advantage of TSV is the shortest chip-to-chip vertical interconnection, which allows for size reduction of the chip and reducing signal transmission delay. Electrodeposition plays an important role in TSV development, especially copper electrodeposition, which is a critical technology and generally used in 3D chip packaging.
In TSV technology, the thermo-mechanical fatigue may lead to the TSV interconnects failures because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The package materials with different CTEs will induce large stresses at the interfaces. In order to overcome this problem, we choose tungsten to substitute copper. However, tungsten cannot be directly plated in an aqueous electrolytes, it can be co-deposited with iron group metals. Nickel-tungsten alloy has excellent corrosion resistance, wear resistance and mechanical strength, which is a favorable candidate.
Traditional process for TSV is dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO2 isolation layer; (3) deposition of a TiN barrier layer and a copper seed layer; (4) electrodeposition of copper inside the via. In our research, we reduce the procedure of TSV using the wet process to substitute barrier and seed layer with CoWP, and electrodeposition with Ni-W alloy to make a copper-free process. In other words, a copper-free TSV with simplified processing steps is fabricated leading to lower fabrication cost, moreover, a low-stress TSV filled with low CTE metals is also fabricated to improve the thermo-mechanical fatigue of TSV leading to better package reliability. The Ni-W alloy was plated using NiSO4 and NaWO4 electrolytes; the additives included suppressor, accelerator, and surfactant. This Ni-W plating formula can achieve bottom-up filling of TSV with an aspect of 3.2 and a diameter of 20μm.
其他識別: U0005-2407201221200300
Appears in Collections:化學工程學系所

Show full item record
TAIR Related Article

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.