Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/37675
標題: Low-power parallel multiplier with column bypassing
作者: Wen, M.C.
王行健
Wang, S.J.
Lin, Y.N.
Project: Electronics Letters
期刊/報告no:: Electronics Letters, Volume 41, Issue 10, Page(s) 581-583.
摘要: 
A low-power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known, is proposed. This design maintains the original array structure Without introducing extra boundary cells, as was the case in previous designs. Experimental results show that it saves 10% of power for random input. Higher power reduction can be achieved if the operands contain more 0's than 1's.
URI: http://hdl.handle.net/11455/37675
ISSN: 0013-5194
DOI: 10.1049/el:20050464
Appears in Collections:資訊科學與工程學系所

Show full item record
 

Google ScholarTM

Check

Altmetric

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.