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|標題:||Low-power BIST with a smoother and scan-chain reorder under optimal cluster size||作者:||Lai, N.C.
|關鍵字:||built-in self-test (BIST);design for testability;low-power design;routing;testing||Project:||Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems||期刊/報告no：:||Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 11, Page(s) 2586-2594.||摘要:||
The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths.
|Appears in Collections:||資訊科學與工程學系所|
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