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|標題:||Zero-aware asymmetric SRAM cell for reducing cache power in writing zero||作者:||Chang, Y.J.
|關鍵字:||asymmetric;cache write power;low power;on-chip caches;SRAM cell;zero-aware||Project:||Ieee Transactions on Very Large Scale Integration (Vlsi) Systems||期刊/報告no：:||Ieee Transactions on Very Large Scale Integration (Vlsi) Systems, Volume 12, Issue 8, Page(s) 827-836.||摘要:||
Most microprocessors employ the on-chip caches to bridge the performance gap between the processor and the main memory. However, the cache accesses usually contribute significantly to the total, power consumption of the chip. Based on the observation that an overwhelming majority of the values written to the cache are "0 ," in this paper we propose a zero-aware SRAM cell with an asymmetric inverter pair, called ZA cell, to minimize the cache power consumption in writing "0." The ZA cell uses a circuit-level technique, which is software independent and orthogonal to other low-power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results based on the SPEC2000 and MediaBench traces show that without compromise of both performance and stability, the ZA cell can reduce the average cache write power consumption over 60% for both the baseline instruction and data caches. In particular, the ZA cell is attractive in the data caches, which reveal the high write-zero rate.
|Appears in Collections:||資訊科學與工程學系所|
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