Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/38643
標題: (VLSI Design:An International Journal of Custom-Chip Design,Simulation and Testing,00(0):001-018)Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis
作者: W. B. Jone
D. C. Huang 
S. C. Chang
S. R. Das
關鍵字: Defect level analysis;Random testing;Pseudorandom testing;Markov model;Di fferential equations
出版社: Malaysia: the Gordon and Breach Science Publishers
Project: VLSI Design:An International Journal of Custom-Chip Design,Simulation and Testing, Volume 0, Issue 0, Page(s) 1-18.
URI: http://hdl.handle.net/11455/38643
Appears in Collections:資訊科學與工程學系所

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