Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/39906
標題: Carrier backscattering characteristics of nanoscale strained complementary metal-oxide-semiconductor devices featuring the optimal stress engineering
作者: Chang, S.T.
張書通
Liao, M.H.
Lee, C.C.
Huang, J.K.
Wang, W.C.
Hsieh, B.F.
關鍵字: ballistic transport;charge injection;CMOS integrated circuits;etching;Ge-Si alloys;MOSFET;nanoelectronics;inversion-layers;mobility;source/drain;transistors;mosfets;channel
Project: Journal of Vacuum Science & Technology B
期刊/報告no:: Journal of Vacuum Science & Technology B, Volume 27, Issue 3, Page(s) 1261-1266.
摘要: 
The authors present stress distribution simulation characterization of the three-dimensional boundary effects and show how these effects can impact the achievable transistor performance gain. The high-performance complementary metal-oxide-semiconductor (CMOS) device has been achieved by stressors such as contact etch stop layer (CESL) and SiGe S/D and optimal geometric structure design. The biaxial-like stress distribution resulting from symmetry structure and uniaxial-like stress distribution resulting from asymmetry structure seems to be promising when considering drive current enhancement, the ballistic efficiency, and carrier injection velocity for CMOS devices. The comprehensive study helps the future nanoscale CMOS device design and demonstrates that the stress enhancement factors remain valid for future technology.
URI: http://hdl.handle.net/11455/39906
ISSN: 1071-1023
DOI: 10.1116/1.3125275
Appears in Collections:光電工程研究所

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