Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/43770
標題: Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips
作者: Y.T.Hwang
W.D.Chen
出版社: Institution of Engineering and Technology
Project: IET Circuits Devices & Systems, Volume 5, Issue 5, Page(s) 424-432.
摘要: 
Complex QR factorisation is a fundamental operation used in various applications such as adaptive beamforming and MIMO signal detection. In this paper, based on Givens rotation scheme, a high-throughput, fully parallel complex-valued QR factorisation (CQRF) design is presented. It features the lowest computing complexity in various factorising schemes and indicates no BER performance loss when applied to a MIMO signal detection system. Via carefully plotted scheduling, one CQRF computation can be completed in eight clock cycles. In hardware design, a low complexity and look-up-table-free CORDIC algorithm is employed to implement the rotation operations. Further design optimisations, such as hardware sharing of common modules and reduction of register usage by shortening the variable's life span, are also applied. Sized 22 and 44 chip designs largely following the IEEE 802.11n standard are developed. The implementation results in TSMC 0.18 um process technology show that the proposed 44 design, with a gate count of only 134.6 K, is capable of performing 15 M CQRFs per second. The measured power consumption is 196.3 mW at 120 MHz. Compound performance indexes such as area-time product and energy consumption per CQRF also indicate significant performance edges of the proposed designs.
URI: http://hdl.handle.net/11455/43770
ISSN: 1751-858X
DOI: 10.1049/iet-cds.2010.0143
Appears in Collections:電機工程學系所

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