Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/43845
標題: A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-mu m CMOS
作者: Yang, Ching-Yuan
Chang, Chih-Hsiang
Weng, Jun-Hong
Wu, Hsin-Ming
關鍵字: Frequency doubler;frequency synthesizer;low voltage;phase rotator;phase-locked loop (PLL);voltage-controlled oscillator (VCO)
出版社: IEEE-INST+ELECTRICAL+ELECTRONICS+ENGINEERS+INC.
Project: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Volume 58, Issue 2, Page(s) 65-69.
摘要: 
To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency for the synthesizer. Additionally, a hybrid circuit utilizing a new folded regime for the first-stage divider and the phase-rotating circuit is developed in the prescaler. Under full-speed operation, the QVCO with the frequency doubler and the divider can work from a 0.5-V supply, whereas the synthesizer dissipates 12 mW. At 9.1-GHz carrier frequency, the measured phase noise is -104.5 dBc/Hz from 1-MHz offset.
URI: http://hdl.handle.net/11455/43845
ISSN: 1549-7747
DOI: 10.1109/TCSII.2010.2092830
Appears in Collections:電機工程學系所

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